Comparison · OpenECOS · OpenROAD · Vibe-IC · verified 2026-08-08

Different layers,
not a scoreboard.

Two projects get named next to Vibe-IC most often: OpenECOS and OpenROAD. Only one of them is even in the same layer of the stack — and the other one is something we depend on and contribute back to. This page states what each project actually does, where the overlap is real, and where Vibe-IC is measurably behind. Everything here was checked against the projects' own repositories and READMEs on 2026-08-08.

Where each project sits Where Vibe-IC is behind

The three projects

What each one actually is

Stated in each project's own terms, from its own README — not in ours.

OpenROAD

The OpenROAD Project · started June 2018 under the DARPA IDEA program · BSD-3-Clause

The reference open-source engine for the physical half of digital design: floorplanning, macro and cell placement, clock-tree synthesis, routing and finishing, driven through a Tcl/Python API. Its stated target is an autonomous, no-human-in-loop 24-hour RTL-to-GDSII turnaround. It is deliberately PDK-independent, and it is the engine underneath ORFS, OpenLane, SiliconCompiler, Hammer and OpenFASoC. Its README claims over 600 tapeouts on SKY130 and GF180.

github.com/The-OpenROAD-Project/OpenROAD

OpenECOS

ECOS Team, Institute of Computing Technology, Chinese Academy of Sciences · PDK by ICsprout IC Co. + Zhejiang University · Apache-2.0 (core repos)

A vertically integrated RTL-to-chip stack: ECOS Studio (a desktop IDE promising an “FPGA-like experience for ASIC design”), the ecc chip compiler (a Python CLI running Yosys → ECC-Tools → KLayout with rtl2gds / rcx / harden / syn_sta flows), ECC-Tools (an iEDA-derived netlist-to-GDS toolchain, MulanPSL-2.0), ecc-dreamplace, an IP catalog, and their own ICsprout55 open 55nm PDK. Their entry point is RTL; the differentiator is that they own the PDK and the shuttle.

github.com/openecos-projects

Vibe-IC

vibeic.ai · Claude Code plugin + MCP-EDA server · Apache-2.0 · first commit 2026-06-13

An AI-agent-driven flow that starts one layer above both of the others: natural-language intent → L1-L27 design documents → RTL → lint / simulation / formal / conformance → synthesis → PnR → DRC / LVS / STA / IR → GDS, with a separate analog A1-A9 and mixed-signal M1-M4 track. It does not implement a placer or a router; it drives OpenROAD, Yosys, OpenSTA, KLayout, Magic, Netgen, ngspice and others inside a forked toolchain image, and gates every step with deterministic checkers so a step cannot report PASS without an artifact.

github.com/vibeic/vibe-ic

Layering · the part that matters most

OpenROAD is upstream of Vibe-IC, not a rival

Vibe-IC runs OpenROAD. The digital PnR, CTS and routing results on this site are produced by OpenROAD inside the ghcr.io/vibeic/vibeic-eda image. We maintain a fork at github.com/vibeic/OpenROAD and push fixes into it — most recently PR #3, merged 2026-08-08, which restored LEF58_SPACING TONOTCHLENGTH: the value was parsed by odb and then silently discarded before it reached TritonRoute's constraint model, so a staged rule produced byte-identical routing to no rule at all. Presenting the engine we depend on as a defeated competitor would be both false and ungrateful. The honest question is which layer each project occupies.

Intent → specification

A human describes a chip in plain language; a machine produces a complete, checkable design document set.

Vibe-IC — L1-L27 documents OpenECOS — none OpenROAD — out of scope

Specification → RTL

Authoring synthesizable HDL, plus lint, simulation, formal and spec-conformance.

Vibe-IC — Phase 2 OpenECOS — partly: AI-generated IP blocks in the catalog OpenROAD — out of scope

Flow orchestration

Sequencing the engines, carrying configuration, deciding what runs next and whether it passed.

Vibe-IC — runner chain + gates OpenECOS — ecc + ECOS Studio OpenROAD — ORFS (sibling repo)

Physical-design engine

The actual algorithms: floorplan, place, CTS, route, optimize. This is where a project either writes a placer or calls one.

OpenROAD — writes it OpenECOS — ECC-Tools (iEDA-derived) + ecc-dreamplace Vibe-IC — calls OpenROAD

Sign-off

DRC, LVS, STA, IR-drop, parasitic extraction against a real deck.

Vibe-IC — KLayout / Magic / Netgen / OpenSTA, gated OpenECOS — RCX + STA in ecc; DRC/LVS rules listed as Todo in the PDK OpenROAD — STA in-tree; DRC/LVS delegated to external tools

PDK & foundry access

Whose process, whose rules, whose shuttle. Nobody in this table manufactures anything themselves.

OpenECOS — owns ICsprout55 (55nm), preview status OpenROAD — PDK-independent by design Vibe-IC — consumes 3 open foundry PDKs, owns none

Read down the stack: the only layer where all three genuinely compete is flow orchestration. Above it, Vibe-IC is alone. Below it, we are a consumer — of OpenROAD's algorithms and of somebody else's silicon.

Side by side · every cell traceable to a public repository

Attribute by attribute

An empty capability is written as “none”, not omitted — including ours. Star counts and commit counts are the projects' GitHub values on 2026-08-08 and will drift.

Attribute OpenROAD OpenECOS Vibe-IC
Layer Physical-design engine Flow + PDK + IP, vertically integrated AI agent above the whole flow
Input you provide A netlist / Verilog + LEF/LIB + a Tcl script RTL + a project config (GUI or CLI) A paragraph of plain language, or design documents
Output DEF / GDSII GDSII (+ RCX / STA reports) Design docs + RTL + testbenches + GDSII + per-gate evidence
Generates RTL No — out of scope Partly
catalog IP only; e.g. axi4-to-apb4-bridge declares “本 IP 的 RTL、验证环境及配套文档由 AI 生成”. The flow itself does not author RTL.		 Yes — the core function
AI / LLM in the flow No LLM. ML used for modelling and prediction. No — ecc and ECOS Studio are scripted / GUI Yes — agent-driven end to end, deterministically gated
Functional verification Out of scope Not in the ecc flow Lint, simulation, formal, coverage, spec-conformance, FPGA prototype
Analog / mixed-signal No — digital only (OpenFASoC is a sibling project) No — digital only Analog A1-A9 and mixed-signal M1-M4 tracks
PDKs PDK-independent; validated on SKY130, GF180, Nangate45, ASAP7 (plus NDA nodes) One node — ICsprout55 (their own 55nm) 3 open foundry PDKs (sky130A, GF180MCU, IHP-SG13G2) + 2 predictive enablements marked tapeout_capable=false + a commercial-PDK mechanism carrying no vendor name in the repo
Proven silicon README claims over 600 tapeouts (SKY130, GF180) retroSoC, a RISC-V SoC, fabricated at 100 MHz on the 55nm process; first ICS55 engineering shuttle scheduled Dec 2025 None. No Vibe-IC design has been fabricated.
Open-benchmark scores None published — not a code-generation tool None published VerilogEval-v2 153/156 · VerilogEval-Human 154/156 · RTLLM v2.0 49/50 · CVDP 243/302
blind, graded by each benchmark's official upstream testbench
Upstream contribution Is the upstream ECC-Tools is iEDA-derived (MulanPSL-2.0); ecc-dreamplace derives from DREAMPlace A tracked fork set (OpenROAD, Yosys, Magic, Netgen, KLayout, ngspice, Icarus, Verilator, OpenSTA, cocotb, sby, ALIGN) with daily upstream sync, each fix carrying a reproducible FAIL→PASS proof
License BSD-3-Clause Apache-2.0 for the core repos; ECC-Tools is MulanPSL-2.0; several IP repos have no license set yet Apache-2.0
Age & scale Since Oct 2019 · 42,723 commits · 2,951 stars · 980 forks ECC-Tools since Jan 2026 · icsprout55-pdk 252 stars · ecos-studio 51 stars · ecc 16 stars Since Jun 2026 · 16 stars · 6 forks

Sources: each project's own README and GitHub API metadata, read on 2026-08-08. The Chinese sentence in the “Generates RTL” row is quoted verbatim from the openecos-projects/axi4-to-apb4-bridge README, which also discloses that the IP has no formal verification, no independent human review, no synthesis sign-off and no silicon validation — a disclosure we think deserves credit rather than a point scored against them.

The honest ledger · both columns, not one

Where we are behind, and where we are actually different

This project's whole doctrine is that a certificate which cannot fail is worthless. A comparison page that only listed our advantages would be exactly that kind of certificate. So the deficits come first, and they are specific.

Where Vibe-IC is behind

  • No tapeout. Not one Vibe-IC design has been fabricated. OpenROAD's README claims over 600; OpenECOS has retroSoC running at 100 MHz on real 55nm silicon. On the axis that ultimately decides whether a flow works, we have nothing to show.
  • We publish a benchmark-IC convergence matrix and most of it is not converged. The live count is below; it is generated from each run's own completion audit, not from a status table, precisely so it cannot be talked upward.
  • We have already published a cell as converged that was not. caravel_user_project × sky130A now reads FAIL on our own evaluation page, because the overclaim was caught and corrected rather than quietly dropped. It is on this page too, because a correction that only appears where nobody looks is not a correction.
  • We own no PDK and no foundry relationship. OpenECOS owns ICsprout55 and its shuttle. We consume other people's open PDKs and depend entirely on their maturity.
  • We write no placement or routing algorithms. OpenROAD's placer, CTS engine and detailed router are the state of the art we consume. If OpenROAD stopped, our Phase 3 would stop with it.
  • Scale. 16 stars and roughly two months of history against OpenROAD's 42,723 commits since 2019 and an ecosystem of downstream flows. Being newer is not a defence; it is just the size of the gap.

Where Vibe-IC is genuinely different

  • It starts from intent, not from RTL. Both other projects require you to already have a design. Vibe-IC turns a paragraph into L1-L27 design documents and then into RTL, and both entry paths — documents or dialogue — converge on the same handoff, so there is no “skip to RTL” back door.
  • Verification is inside the flow, not beside it. Lint, simulation, formal, coverage, spec-conformance and an FPGA prototype are steps the gate requires, not optional extras a user remembers to run.
  • Multi-PDK portability. The same design is driven onto sky130A, GF180MCU and IHP-SG13G2, which is what turns “it worked once” into “the flow is portable”. Both other projects are effectively single-target in practice.
  • An analog and mixed-signal track. A1-A9 and M1-M4 exist because most real chips are not purely digital. Neither of the other two addresses analog at all.
  • It is measured on other people's benchmarks. VerilogEval-v2, VerilogEval-Human, RTLLM and CVDP are run blind and graded by their own upstream testbenches — a number somebody else's harness produced, not one we defined. Neither of the other two publishes such a score.
  • The fixes go back upstream. Driving an agent through these tools exposes bugs a human flow never reaches — a parsed-then-discarded LEF58 rule, a silently inert constraint, a batch simulator returning success on a failed measurement. Each becomes a fork commit with a reproducible FAIL→PASS proof, and where possible a pull request.
  • Failures are published. The repository carries a fail-case ledger and a residual-defects file, and a re-run never overwrites an older verdict, so a regression stays visible instead of being replaced.

Our current standing · generated from landed evidence

The number this page is judged by

A comparison page is easy to write and easy to leave standing after it stops being true. This block is not written by hand: it is regenerated from each benchmark run's own completion audit in the public repository, by the same generator that feeds the Evaluation page. If our position gets worse, this gets worse — on its own, without anyone deciding to update it.

4 of 12 (IC × PDK) cells converged

IC PDK State Evidence
spmIHP-SG13G2convergedPASS_WITH_WAIVERS · plugin v1.5.58
spmsky130AconvergedPASS_WITH_WAIVERS · plugin v1.10.18
spmGF180MCUconvergedPASS_WITH_WAIVERS · plugin v1.9.96
sha256sky130Ain progressno landed evidence yet
caravel_user_projectsky130Alanded, not convergedFAIL · plugin v1.9.43
edge_llm_accelNanGate45in progressno landed evidence yet
edge_llm_matmul_accelNanGate45in progressno landed evidence yet
ibexsky130Ain progressno landed evidence yet
opentitan_aessky130Ain progressno landed evidence yet
subservientsky130Ain progressno landed evidence yet
subservientGF180MCUin progressno landed evidence yet
u_hawaii_adcsky130AconvergedPASS · plugin v1.9.86

A cell counts as converged only when its landed evidence says so — the verdict is read from the run's own completion audit, not from a status table. Cells with no landed evidence show as in progress; they are never counted as passing and never removed from the denominator. Updated 2026-08-12 15:17 UTC+08:00.

Neither OpenROAD nor OpenECOS publishes an equivalent per-design convergence table, so this row of the comparison has no counterpart column — which is itself worth stating plainly rather than presenting as a win.

Check it yourself

Every claim on this page points at a public repository. Read theirs, read ours, and if a cell here is wrong, the fastest way to correct it is an issue.

How Vibe-IC is measured

Related: the EDA fork ledger, where each upstream fix is tracked with its proof.