The Complete Flow · Spec → Silicon
One automated flow across 3 Phases · 5 Stages · 63 Steps — natural-language spec → L1–L27 structured docs → RTL → synthesis → physical design → sign-off → GDSII → manufacturing test. Every step is program-first, cross-checked by an AI expert, and held by a compliance gate.
This page is the Overview + every step. The flow is one automated pipeline: a natural-language spec becomes L1–L27 structured docs, then RTL, then a synthesized netlist, then a physical layout, then a signed-off GDSII, then manufactured and tested silicon. Every step is program-first (a deterministic program runs it), cross-checked by the IC-Expert AI, and held by a compliance gate before the flow advances. Each step below shows four things:
Resources
The complete handbook — install, quick start, every command, the design philosophy, the forked-tool comparison, and benchmark results.
Available13 episodes — each covers a few steps and explains what they do with plain, easy examples.
Live · 13 episodesUnder the hood
The physical & verification steps run on an enhanced open-source EDA toolchain (vibeic-eda) — forks of these tools with patched, proven fixes. Each chip links to the repo (OpenSTA and Xschem ship from the base toolchain — linked upstream):
Every step, input, output, tool and gate on this page is traceable to the Vibe-IC flow runner and its compliance gates — nothing is invented (steps 40–44 are external foundry/OSAT, not run by the flow). This is a bet and an exploration: not yet tape-out-ready, not a replacement for commercial EDA, and not formally expert-reviewed — the limits are documented on the blog.