D1 Wiring
Is a real gate named and connected to the step?
The Complete Flow · Spec → Silicon
Three main phases and two conditional tracks cover structured documents, RTL, synthesis, physical design, sign-off, output, and external manufacturing and test. The current flow declares 70 steps across five main stages, plus analog and mixed-signal stages. A declared step or gate is not a chip PASS.
Phase 1 turns dialogue and supplied design documents into L1–L27 structured documents. Phase 2 builds and verifies RTL, constraints, synthesis and test logic. Phase 3 implements the physical design, checks sign-off, delivers GDS and hardmacro artifacts, then records external manufacturing and test. Analog A1–A9 and mixed-signal M1–M4 run when the design needs them.
The 350 recomputed cells cover D1, D2, D5, D6 and D8. D3 has no completed run supplied; D4 and D7 need semantic review; D9 has no published run corpus in this census. The grid command returning zero for its recomputed scope is not a 630-cell PASS.
Phase 1 produces structured L documents from the supplied design input. Phase 2 consumes those documents to produce RTL, constraints, verification results and a synthesized netlist. Phase 3 consumes that netlist and the declared physical inputs to produce layout, sign-off reports and release artifacts. Each transition depends on its required evidence and gate verdict; a declared output alone does not establish a successful handoff.
The declared open-source tool stack includes Yosys, OpenROAD, OpenSTA, Icarus Verilog, Verilator, SymbiYosys, ABC, KLayout, Magic, Netgen and ngspice. The row inventory below records tools found in program source; it does not prove that each tool ran for a given design.
Open-source tool forksThe existing 15-part video series remains available in Chinese on YouTube and in English on Vimeo. It explains the three phases, the two conditional tracks, and the gate questions.
YouTube · 中文 · Vimeo · EnglishThese dimensions check whether our flow gates exist, can fail, and affect the final process verdict. They do not prove the design is correct. Source declarations, runtime consumers and final artifacts are separate evidence.
Is a real gate named and connected to the step?
Can the step fail on a design-content defect?
Did this run actually produce its declared outputs?
Does the check measure what its claim says?
Are the declared upstream edges complete and acyclic?
Are conditional skips and vacuous passes disclosed?
Are all emitted artifacts declared?
Will a missing declared output block progress?
Does a step failure reach overall FAIL and a nonzero exit?
D9 follows one specific chain: the step’s own FAIL → step FAIL → overall FAIL → nonzero process exit. A gate that merely prints a failure is insufficient. For D4 and D7, a green structural proxy cannot replace a judgement about the real property or a complete output inventory.
An earlier gate page reported an older 68-step snapshot and mutation results from that snapshot. Those historic counts are not applied to this 70-step census. The current cells below retain unknown and missing evidence as missing.
A 2026-08-28 mutation probe of the older gate suite made five dimensions reject their own injected defect and found four misses. A separate content-only mutation kept structural checks green. These are historical findings that explain why the nine questions and a green grid cannot certify output correctness; they are not fresh 70-step measurements.
The PPA layer can measure, normalize, search candidates, track provenance and guard rollback. Individual measured repair paths and declared controller edges are different inventories. An executable component alone does not prove that every flow edge is bound to a controller or that every affected step is remeasured.
Read the detailed PPA reviewExplore execution policy targets and the reviewed useful tool catalog for all 70 steps.
v1.26.86 remains released at 9ec8b3fdf. The exact enhancement70 candidate cea657a11 failed its scoped shipping gate: 566 failures and 20 errors; source repairs are in progress. The separate native current-call lifecycle passed a fresh real-container measurement at d244cccbd. Enhancement70 is not yet released.
| Scope | Recorded fact |
|---|---|
| Current release | v1.26.86 / 9ec8b3fdf is released: source-bound RTL audit applicability. Exact release gate: 1066 passed, 1 skipped, 5 xfailed, 3 xpassed, 0 plain failures; write guard passed. PR #2862 is merged and issue #2847 is closed. The earlier v1.26.85 release landed the runtime guard and Python 3.12 scanner fix, closing #2863. |
| Historical v83 foundation gate | v1.26.83 / PR2865: original G9857 passed / raw0, 518 skipped, 3 xfailed; T52 passed / raw0; M unselected. Historical exact landed component scope. |
| Default mode | When unspecified, automatically choose one default plan per step: applicable LibreLane → OpenROAD → other useful existing tools. The program selects the tool with AI assistance. Promote a tool only with better qualifying evidence on typed identical current INPUT. Custom implementation is last when no useful applicable tool exists. |
| Ultra mode | Use as many feasible useful distinct tools concurrently as available for the step; actual independent AI selection must bind exact qualifying artifacts and the current request. Wrappers around one engine are one tool; a fixed ENGINES array proves no issued arms. Two licensed mappers are not required. Name available providers, complementary tools and unavailable alternatives. |
| Recorded source inventory | Source snapshot 299bd782: 70 registered factories; 62 resolved controller hooks and 8 unresolved rows. Each factory currently supplies one complete producer path; distinct-tool Ultra factory integration remains open. Source registration and native execution are recorded separately. |
| Finite functional evidence | Exact cb286d437 SOURCE_FIXTURE scope: 7 A1 + 23 FX controls, 30 passed in 172.55 s. The isolated reverse control produced the expected 2 failures in 18.52 s; both write guards passed. These are 30 acceptance controls, not 30 completed steps. Earlier A1 and Step9 default examples remain historical component evidence. |
| Metrics84 | The repaired release gate passed: 3473 passed, 37 skipped, 1 xfailed, raw0. T/M unselected; 34 nightly nodes NOT_RUN / no credit. The original seven failures remain historical; v1.26.84 is released. |
| Accepted software repairs | Accepted scoped repairs: typed default promotion (10 same-INPUT/objective/binding software cases); Step3 caller before four mandatory consumers (captured-boundary input); backend callback context helper/decorator (toy callables 31/37). The backend control exercised no worker execution or native boundary. These scopes establish neither whole-producer/native execution, independent AI best-artifact adoption nor complete step/full70 qualification. |
| Enhancement repair status | The exact cea657a11 / tree ffff74d44 shipping candidate ran 5061 passing tests, 566 failing tests, 20 errors and 88 skips in 1217.27 s; the write guard passed. These are test outcomes, not completed or remaining step counts. Actual captured causes are being repaired: consumed-input preflight, host placement and reentry, two Docker memory-limit sites, and a signoff subprocess fixture signature. Earlier trials remain historical evidence. |
| Source repair progress | The controller shipping candidate includes classifier repairs and the Step30 single-simulator default. Its final gate failed and the branch remains unlanded. A separate Step30 ngspice/Xyce per-tool factory source package passed four canonical scoped controls at cdc84010; complete simulator arms and best-artifact selection remain unmeasured. Full SPM/Subservient reruns remain deferred until enhancement completion and publication. |
| Native and release layers | Fresh native current-call evidence at d244cccbd / tree 31822abf: handshake ACK, install, dispatch-site authorization, revoke, scope exit, and refusal of reuse all passed. The real container, worker and outer process exited zero with finite kernel resource limits and a pinned image. This two-file source package is separate from the failed controller shipping tree and does not qualify every step or the complete Ultra path. |
| Retained physical results | Historical RCX SS hold -0.0397 ns / 3 OPEN; CUT20 area 5.508835% FAIL, delay INCONCLUSIVE; SPM LVS FAIL; IC 0/2. No new IC sign-off run. |
| Catalog and reference | 70 steps / 63 tools / 333 recommendations / 433 HARVEST references preserved. Exact owner old HTML is layout / September25 history only; current facts come from bound collector and ROOT receipts. |
Pinned release source · Defaults and prerequisites · Canonical flow · Download status and source bindings
The program chooses one applicable integrated primary path: LibreLane, then OpenROAD, then another proven tool; own programs cover remaining work. An exact-input, qualified better result can override this priority. AI assists configuration, interpretation and repair; the program owns source binding and acceptance.
Run applicable independent candidate paths concurrently on the same frozen inputs, within CPU, memory and license limits. Keep dependent components in order. Validate every candidate, then let AI recommend the best qualifying artifact against the declared objective; the program records and adopts the accepted choice.
These are execution policy targets, not a completed Ultra controller or a run PASS. Integrated in pinned source means a source-integrated adapter; historical executable presence alone is insufficient. This inventory did not re-run the steps. AI can recommend only qualifying artifacts. Missing evidence, conflicting sign-off or a failed required checker still block adoption.
LibreLane orchestrates components such as OpenROAD and OpenSTA. A flow and the engine it calls belong to the same evidence path; counting both does not create independent confirmation. Tool candidates are role-specific and must satisfy their declared applicability.
Phase 1 Doc Extraction (17 skills + dialogue entry → L1-L27). Inputs: phase1/input_prompt/* OR phase1/input_doc/* OR input/docs/* OR input/phase1_prompt.md OR input/phase1_structured.yaml. Outputs: phase1/generated_docs/L1_DATASHEET.json; phase1/generated_docs/L2_FRS.json; phase1/generated_docs/L3_CMD_PROTOCOL.json; phase1/generated_docs/L4_REGMAP.json; phase1/generated_docs/L5_ADI_SPEC.json; phase1/generated_docs/L6_CONTROL_LOGIC.json; phase1/generated_docs/L7_TEST_DEBUG.json; phase1/generated_docs/L8_TIMING_WAVEFORM.json; phase1/generated_docs/L8_RTL_CONSTANTS.json; phase1/generated_docs/L9_INTEGRATION_SPEC.json; phase1/generated_docs/L10_TEST_CASES.json; phase1/generated_docs/L11_OTP_CONTENT.json; phase1/generated_docs/L12_BEHAVIORAL_SEQUENCES.json; phase1/generated_docs/L13_*.json; phase1/generated_docs/L19_CONSTRAINTS_PDK.json; phase1/generated_docs/L21_POWER_INTENT.json; reports/phase1/extraction_coverage_report.md; reports/phase1/extraction_coverage_report.json; reports/audit/phase1/expert_parse_track.json; phase1/extraction_patterns.json.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 3 references; destinations: librelane_config, vibeic_gate. Existing disposition retained.
execution_frontend_worker.py:contract · execution_frontend_worker.py:required_input_specs · Public facts and HARVEST destinations
Vibe-IC program and evidence gates · Poppler pdftotext · Tesseract
Mode: direct_adapter · Source / existing records checked
This inventory did not re-run or certify this step.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
Vibe-IC program and evidence gates
Components: Poppler pdftotext · Tesseract
Integrated in pinned source
Policy target; not a newly deployed mode controller.
Source-bound extraction with file-appropriate text/OCR tools
No LibreLane/OpenROAD spec-extraction engine exists.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →Submission Template Ingest — the operator's slot geometry and fixtures (chip/IC path only). Inputs: the shuttle operator's published project template — the repository or archive that pins the slot geometry, ships the die-identification fixtures, and lists the pads for each slot. Declared as external and unprobed because it is fetched, not produced, and the flow must be able to say it was never fetched.. Outputs: input/submission_template/slots/*.yaml OR input/submission_template/NO_TEMPLATE.txt OR input/submission_template/SELF_TAPEOUT.txt; reports/phase1/submission_template.json; input/submission_template/tapeout_declaration.json; reports/phase1/tapeout_declaration.json.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 4 references; destinations: librelane_config, vibeic_gate. Existing disposition retained.
execution_frontend_worker.py:contract · execution_frontend_worker.py:required_input_specs · Public facts and HARVEST destinations
Vibe-IC program and evidence gates · KLayout
Mode: direct_adapter · Source / existing records checked
This inventory did not re-run or certify this step.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
Vibe-IC program and evidence gates
Components: KLayout
Integrated in pinned source
Policy target; not a newly deployed mode controller.
Operator template ingestion and geometry refusal
No external engine covers operator fetch/normalization.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →Spec-to-RTL. Inputs: D1. Outputs: phase2/stage1/rtl/*.sv OR phase2/stage1/rtl/*.v.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 4 references; destinations: librelane_config, vibeic_gate, drop. Existing disposition retained.
execution_frontend_worker.py:contract · execution_frontend_worker.py:required_input_specs · Public facts and HARVEST destinations
Vibe-IC program and evidence gates
Mode: program_only · Source / existing records checked
This inventory did not re-run or certify this step.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
Vibe-IC program and evidence gates
Components: Yosys
Integrated in pinned source
Policy target; not a newly deployed mode controller.
Program-driven RTL authoring with AI assistance
No LibreLane/OpenROAD arbitrary spec-to-RTL authoring engine.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →🔁 RTL validation (rewrite fidelity + lint + Quartus-unsafe patterns + RTL-bug claim schema). Inputs: phase2/stage1/rtl/*.sv OR phase2/stage1/rtl/*.v. Outputs: reports/phase2/lint/rtl_hygiene.json; reports/phase2/lint/rom_init_lint.json; reports/crosslayer/rewrite_equivalence_check.json.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 8 references; destinations: vibeic_gate, drop. Existing disposition retained.
execution_frontend_worker.py:contract · execution_frontend_worker.py:required_input_specs · Public facts and HARVEST destinations
Vibe-IC program and evidence gates · Yosys
Mode: direct_adapter · Source / existing records checked
This inventory did not re-run or certify this step.
Opt-in source paths; not the production default: slang / slang-tidy / pyslang
Own hygiene rules are default; optional pyslang semantic check and Yosys rewrite-fidelity proof are separate. Dedicated Verible/svck executables are not current adapters.
Optional pyslang path in rtl_hygiene_lint.py; not a mandatory primary linter
LibreLane
Components: Verilator · Yosys
Proposed integration
Policy target; not a newly deployed mode controller.
LibreLane Verilator lint and elaboration audit
Prefer applicable LibreLane orchestration; preserve mandatory complementary checks and uncovered intent rules.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →🔁 CDC / RDC check. Inputs: phase2/stage1/rtl/*.sv OR phase2/stage1/rtl/*.v. Outputs: reports/phase2/cdc/crossing.json; reports/phase2/cdc/async_input.json; reports/phase2/cdc/reset_dep.json.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 4 references; destinations: vibeic_gate, drop. Existing disposition retained.
execution_frontend_worker.py:contract · execution_frontend_worker.py:required_input_specs · Public facts and HARVEST destinations
Vibe-IC program and evidence gates
Mode: program_only · Source / existing records checked
This inventory did not re-run or certify this step.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
LibreLane
Components: Yosys · Vibe-IC program and evidence gates
Proposed integration
Policy target; not a newly deployed mode controller.
LibreLane netlist facts plus CDC/RDC intent checks
Prefer applicable LibreLane orchestration; preserve mandatory complementary checks and uncovered intent rules.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →🔁 Simulation (testbench-based + L10/L12 coverage + Verilator coverage). Inputs: phase2/stage1/rtl/*.sv OR phase2/stage1/rtl/*.v; phase1/generated_docs/L10_TEST_CASES.json; phase1/generated_docs/L12_BEHAVIORAL_SEQUENCES.json. Outputs: phase2/stage1/sim/*.log OR phase2/stage1/sim/results.xml OR phase2/stage1/sim/pass.flag OR phase2/stage1/sim_professional/**/results.xml; reports/phase2/coverage/coverage_actual.json; reports/phase2/coverage/coverage_verilator.json.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 5 references; destinations: fork_patch:vibeic/verilator, vibeic_gate, librelane_custom_step. Existing disposition retained.
execution_frontend_worker.py:contract · execution_frontend_worker.py:required_input_specs · Public facts and HARVEST destinations
Icarus Verilog / vvp · Verilator · cocotb · pyuvm / cocotb-coverage
Mode: direct_adapter · Source / existing records checked
This inventory did not re-run or certify this step.
Opt-in source paths; not the production default: Verilator
Source supports Icarus and explicitly selected Verilator simulator paths plus cocotb/coverage scaffolding; this is not an assertion that all engines run by default.
Explicit compiled-simulator/coverage path; not simultaneous default simulation
Icarus Verilog / vvp
Components: cocotb
Integrated in pinned source
Policy target; not a newly deployed mode controller.
Icarus simulation with substantive testbench grading
LibreLane has no substantive functional-testbench simulator step.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →🔁 Formal verification (assertions proved + bit-level full-stack phase2/stage1/tb). Inputs: phase2/stage1/rtl/*.sv OR phase2/stage1/rtl/*.v. Outputs: phase2/stage1/formal/*.sby OR phase2/stage1/formal/formal_authoring_request.json OR phase2/stage1/formal/formal_not_applicable.json; phase2/stage1/formal/results.json OR phase2/stage1/formal/formal_authoring_request.json OR phase2/stage1/formal/formal_not_applicable.json; phase2/stage1/sim_full_stack/results.json.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 6 references; destinations: vibeic_gate, fork_patch:vibeic/yosys. Existing disposition retained.
execution_frontend_worker.py:contract · execution_frontend_worker.py:required_input_specs · Public facts and HARVEST destinations
SymbiYosys (SBY) · ABC · Yosys · Icarus Verilog / vvp
Mode: direct_adapter · Source / existing records checked
This inventory did not re-run or certify this step.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
SymbiYosys (SBY)
Components: Yosys · ABC
Integrated in pinned source
Policy target; not a newly deployed mode controller.
SBY unbounded proof with a supported engine
No equivalent LibreLane assertion-proof flow.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →FPGA early prototype + verification report audit. Inputs: phase2/stage1/rtl/*.sv OR phase2/stage1/rtl/*.v. Outputs: phase2/stage1/fpga/output_files/*.sof; phase2/stage1/fpga/output_files/*.map.rpt; reports/phase2/fpga/quartus_map_audit.json.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 3 references; destinations: vibeic_gate. Existing disposition retained.
execution_frontend_worker.py:contract · execution_frontend_worker.py:required_input_specs · Public facts and HARVEST destinations
Quartus Prime
Mode: direct_adapter · Source / existing records checked
This inventory did not re-run or certify this step.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
Quartus Prime
Tool / adapter needed
Policy target; not a newly deployed mode controller.
Quartus compile for the declared FPGA target
LibreLane/OpenROAD implement ASICs, not this FPGA target.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →Constraint setup (SDC + PVT matrix). Inputs: phase1/generated_docs/L8_TIMING_WAVEFORM.json; phase2/stage1/rtl/*.sv OR phase2/stage1/rtl/*.v. Outputs: phase2/stage2/constraints/*.sdc; phase2/stage2/constraints/pvt_matrix.json.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 7 references; destinations: librelane_config, fork_patch:vibeic/librelane, vibeic_gate, drop. Existing disposition retained.
execution_frontend_worker.py:contract · execution_frontend_worker.py:required_input_specs · Public facts and HARVEST destinations
Vibe-IC program and evidence gates
Mode: program_only · Source / existing records checked
This inventory did not re-run or certify this step.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
LibreLane
Components: OpenSTA · Vibe-IC program and evidence gates
Proposed integration
Policy target; not a newly deployed mode controller.
LibreLane base SDC and declared PVT configuration
Prefer applicable LibreLane orchestration; preserve mandatory complementary checks and uncovered intent rules.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →🔁 SDC validation. Inputs: phase2/stage2/constraints/*.sdc; phase2/stage2/constraints/pvt_matrix.json; phase1/generated_docs/L8_TIMING_WAVEFORM.json. Outputs: reports/phase2/sdc_check.json.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 5 references; destinations: vibeic_gate. Existing disposition retained.
execution_frontend_worker.py:contract · execution_frontend_worker.py:required_input_specs · Public facts and HARVEST destinations
Vibe-IC program and evidence gates
Mode: program_only · Source / existing records checked
This inventory did not re-run or certify this step.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
LibreLane
Components: OpenSTA · Vibe-IC program and evidence gates
Proposed integration
Policy target; not a newly deployed mode controller.
LibreLane SDC checks and timing-engine validation
Prefer applicable LibreLane orchestration; preserve mandatory complementary checks and uncovered intent rules.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →Synthesis (Yosys → mapped netlist). Inputs: input/submission_template/tapeout_declaration.json; phase2/stage1/rtl/*.sv OR phase2/stage1/rtl/*.v. Outputs: phase2/stage2/synth/netlist.v; phase2/stage2/synth/area.rpt OR phase2/stage2/synth/stats.json.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 13 references; destinations: fork_patch:vibeic/librelane, vibeic_gate, drop, librelane_config. Existing disposition retained.
Recorded canonical source: area_total_vs_budget_check · Recorded canonical source: provenance_check · Recorded canonical source: synth_netlist_check · Public facts and HARVEST destinations
Yosys · ABC · slang SystemVerilog frontend for Yosys
Mode: direct_adapter · Source / existing records checked
This inventory did not re-run or certify this step.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
LibreLane
Components: Yosys · ABC
Proposed integration
Policy target; not a newly deployed mode controller.
LibreLane Yosys.Synthesis
Prefer applicable LibreLane orchestration; preserve mandatory complementary checks and uncovered intent rules.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →🔁 Pre-layout STA (multi-corner). Inputs: phase2/stage2/synth/netlist.v; phase2/stage2/constraints/*.sdc; phase2/stage2/constraints/pvt_matrix.json. Outputs: phase3/stage3/sta/pre_pnr_timing.rpt; reports/phase3/sta/pre_pnr_summary.json.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 7 references; destinations: drop, vibeic_gate. Existing disposition retained.
execution_frontend_worker.py:contract · execution_frontend_worker.py:required_input_specs · Public facts and HARVEST destinations
OpenSTA
Mode: direct_adapter · Source / existing records checked
This inventory did not re-run or certify this step.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
LibreLane
Components: OpenSTA
Proposed integration
Policy target; not a newly deployed mode controller.
LibreLane OpenROAD.STAPrePNR
Prefer applicable LibreLane orchestration; preserve mandatory complementary checks and uncovered intent rules.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →DFT insertion (scan chain + ATPG + at-speed + BSDL). Inputs: phase2/stage2/synth/netlist.v. Outputs: phase2/stage2/dft/scan_netlist.v; phase2/stage2/dft/atpg_coverage.rpt; phase2/stage2/dft/transition_atpg_plan.md; reports/phase2/dft/coverage.json; reports/phase2/dft/bsdl_plan.json; phase2/stage2/dft/coverage.yml.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 12 references; destinations: fork_patch:fault, librelane_custom_step, vibeic_gate. Existing disposition retained.
execution_frontend_worker.py:contract · execution_frontend_worker.py:required_input_specs · Public facts and HARVEST destinations
Fault DFT · Yosys · Icarus Verilog / vvp
Mode: direct_adapter · Source / existing records checked
This inventory did not re-run or certify this step.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
Fault DFT
Components: Yosys · Icarus Verilog / vvp
Integrated in pinned source
Policy target; not a newly deployed mode controller.
Fault scan and ATPG, with explicit missing-obligation checks
LibreLane has no complete DFT/ATPG step.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →ISO-26262 FMEDA diagnostic-coverage (fault-injection; safety designs only). Inputs: phase2/stage1/rtl/*.sv OR phase2/stage1/rtl/*.v. Outputs: .
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 4 references; destinations: vibeic_gate. Existing disposition retained.
execution_frontend_worker.py:contract · execution_frontend_worker.py:required_input_specs · Public facts and HARVEST destinations
Icarus Verilog / vvp
Mode: direct_adapter · Source / existing records checked
This inventory did not re-run or certify this step.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
Yosys
Components: Icarus Verilog / vvp · Vibe-IC program and evidence gates
Proposed integration
Policy target; not a newly deployed mode controller.
Yosys mutation fault list with graded injection
No LibreLane FMEDA engine; use proven fault generation plus the safety grader.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →Transition-delay-fault (at-speed LOC) ATPG. Inputs: . Outputs: reports/phase2/dft/transition_coverage.json.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 5 references; destinations: fork_patch:vibeic/yosys, drop, vibeic_gate. Existing disposition retained.
execution_frontend_worker.py:contract · execution_frontend_worker.py:required_input_specs · Public facts and HARVEST destinations
Fault DFT · Yosys
Mode: direct_adapter · Source / existing records checked
This inventory did not re-run or certify this step.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
Yosys
Components: Fault DFT · Vibe-IC program and evidence gates
Integrated in pinned source
Policy target; not a newly deployed mode controller.
SAT-based LOC transition ATPG
No LibreLane or OpenROAD LOC ATPG engine.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →Post-DFT optimization (resynth / buffering). Inputs: phase2/stage2/dft/scan_netlist.v. Outputs: phase2/stage2/synth/post_dft_netlist.v.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 3 references; destinations: vibeic_gate, drop. Existing disposition retained.
execution_frontend_worker.py:contract · execution_frontend_worker.py:required_input_specs · Public facts and HARVEST destinations
Yosys
Mode: direct_adapter · Source / existing records checked
This inventory did not re-run or certify this step.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
LibreLane
Components: Yosys
Proposed integration
Policy target; not a newly deployed mode controller.
LibreLane Yosys.Resynthesis where scan topology is preserved
Prefer applicable LibreLane orchestration; preserve mandatory complementary checks and uncovered intent rules.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →🔁 Equivalence check (RTL ≡ post-DFT netlist). Inputs: phase2/stage1/rtl/*.sv OR phase2/stage1/rtl/*.v; phase2/stage2/synth/post_dft_netlist.v. Outputs: reports/lec.rpt; reports/lec.json.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 8 references; destinations: fork_patch:vibeic/librelane, vibeic_gate, librelane_config, drop. Existing disposition retained.
execution_frontend_worker.py:contract · execution_frontend_worker.py:required_input_specs · Public facts and HARVEST destinations
Yosys
Mode: direct_adapter · Source / existing records checked
This inventory did not re-run or certify this step.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
LibreLane
Components: EQY · Yosys
Proposed integration
Policy target; not a newly deployed mode controller.
LibreLane Yosys.EQY equivalence arm
Prefer applicable LibreLane orchestration; preserve mandatory complementary checks and uncovered intent rules.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →🔁 Synthesis handoff gate (pre-PnR Yosys script + netlist audit; open-source-flow specific). Inputs: phase2/stage2/synth/netlist.v. Outputs: phase2/stage2/synth/netlist.v; reports/analog/stage_analog_compliance.json.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 5 references; destinations: vibeic_gate, drop. Existing disposition retained.
execution_adapters_release.py:population · execution_adapters_release.py:declared_identities · Public facts and HARVEST destinations
Vibe-IC program and evidence gates
Mode: program_only · Source / existing records checked
This inventory did not re-run or certify this step.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
LibreLane
Components: Yosys · Vibe-IC program and evidence gates
Proposed integration
Policy target; not a newly deployed mode controller.
LibreLane synthesis receipt plus handoff audit
Prefer applicable LibreLane orchestration; preserve mandatory complementary checks and uncovered intent rules.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →Path-delay-fault (at-speed, timing-graded) ATPG. Inputs: . Outputs: reports/phase2/dft/path_delay_coverage.json.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 5 references; destinations: fork_patch:yosys, librelane_custom_step, vibeic_gate. Existing disposition retained.
execution_frontend_worker.py:contract · execution_frontend_worker.py:required_input_specs · Public facts and HARVEST destinations
OpenSTA · Yosys
Mode: direct_adapter · Source / existing records checked
This inventory did not re-run or certify this step.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
Yosys
Components: OpenSTA · Vibe-IC program and evidence gates
Integrated in pinned source
Policy target; not a newly deployed mode controller.
SAT path-delay ATPG with real timing grading
No LibreLane/OpenROAD path-delay ATPG generator.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →Small-delay-defect (SDD) at-speed grade. Inputs: . Outputs: reports/phase2/dft/sdd_coverage.json.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 4 references; destinations: librelane_custom_step, vibeic_gate. Existing disposition retained.
execution_frontend_worker.py:contract · execution_frontend_worker.py:required_input_specs · Public facts and HARVEST destinations
OpenSTA · Yosys · Vibe-IC program and evidence gates
Mode: direct_adapter · Source / existing records checked
This inventory did not re-run or certify this step.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
Yosys
Components: OpenSTA · Vibe-IC program and evidence gates
Integrated in pinned source
Policy target; not a newly deployed mode controller.
SAT pattern population with small-delay grading
No existing full SDD engine in LibreLane/OpenROAD.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →Structural-RTL pre-flight (chip-AGNOSTIC structural gates). Inputs: phase2/stage1/rtl/*.sv OR phase2/stage1/rtl/*.v. Outputs: .
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 6 references; destinations: drop, vibeic_gate. Existing disposition retained.
execution_frontend_worker.py:contract · execution_frontend_worker.py:required_input_specs · Public facts and HARVEST destinations
Vibe-IC program and evidence gates · Icarus Verilog / vvp
Mode: direct_adapter · Source / existing records checked
This inventory did not re-run or certify this step.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
LibreLane
Components: Yosys · Verilator · Vibe-IC program and evidence gates
Proposed integration
Policy target; not a newly deployed mode controller.
LibreLane RTL facts/lint with structural preflight gates
Prefer applicable LibreLane orchestration; preserve mandatory complementary checks and uncovered intent rules.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →Analog Spec Extraction. Inputs: phase1/generated_docs/L1_DATASHEET.json; phase1/generated_docs/L5_ADI_SPEC.json. Outputs: phase3/analog/*/spec.json OR phase1/analog/*/spec.json.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 2 references; destinations: vibeic_gate. Existing disposition retained.
execution_adapters_analog.py:project_population · execution_adapters_analog.py:adoption_destinations · Public facts and HARVEST destinations
Vibe-IC program and evidence gates
Mode: program_only · Source / existing records checked
This inventory did not re-run or certify this step.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
Vibe-IC program and evidence gates
Integrated in pinned source
Policy target; not a newly deployed mode controller.
Source-bound analog specification extraction
No LibreLane/OpenROAD analog-spec extractor.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →Analog Topology Selection. Inputs: phase3/analog/*/spec.json OR phase1/analog/*/spec.json. Outputs: phase3/analog/*/topology.md OR phase2/analog/*/topology.md.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 5 references; destinations: vibeic_gate. Existing disposition retained.
execution_adapters_analog.py:project_population · execution_adapters_analog.py:adoption_destinations · Public facts and HARVEST destinations
Vibe-IC program and evidence gates
Mode: program_only · Source / existing records checked
This inventory did not re-run or certify this step.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
Vibe-IC program and evidence gates
Components: ngspice / XSPICE
Integrated in pinned source
Policy target; not a newly deployed mode controller.
Explicit topology choice with the existing bounded sizing path
No source-integrated external topology selector is proven for the current circuit. PyOPUS is a proposed parameter optimizer, not a replacement for topology selection; adopt it only after compatible simulator/target measurements.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →Analog Netlist Generation. Inputs: phase3/analog/*/topology.md OR phase2/analog/*/topology.md; the PDK device models / tech decks (PDK_ROOT — outside the project tree). Outputs: phase3/analog/*/*.sp OR phase2/analog/*/*.sp.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 6 references; destinations: vibeic_gate, fork_patch:ngspice. Existing disposition retained.
execution_adapters_analog.py:project_population · execution_adapters_analog.py:adoption_destinations · Public facts and HARVEST destinations
ngspice / XSPICE
Mode: direct_adapter · Source / existing records checked
This inventory did not re-run or certify this step.
Runner analog_one_shot_runner.py:1048-1068 passes --verify-sim to analog_a3_netlist_emit.py; ngspice is validation, own program is netlist producer.
Vibe-IC program and evidence gates
Components: ngspice / XSPICE
Integrated in pinned source
Policy target; not a newly deployed mode controller.
Current topology-to-SPICE producer with ngspice validation
The source-integrated netlist emitter covers the current topology. Xschem requires an authored schematic/adapter and has no same-input producer evidence; retain it as an ultra proposed netlisting arm.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →Analog Corner Sweep (PVT). Inputs: phase3/analog/*/*.sp OR phase2/analog/*/*.sp; phase3/analog/*/spec.json OR phase1/analog/*/spec.json. Outputs: phase3/analog/*/corner_results.json OR phase2/analog/*/corner_results.json.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 8 references; destinations: vibeic_gate, fork_patch:ngspice. Existing disposition retained.
execution_adapters_analog.py:project_population · execution_adapters_analog.py:adoption_destinations · Public facts and HARVEST destinations
ngspice / XSPICE
Mode: direct_adapter · Source / existing records checked
This inventory did not re-run or certify this step.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
ngspice / XSPICE
Components: Vibe-IC program and evidence gates
Integrated in pinned source
Policy target; not a newly deployed mode controller.
Current ngspice corner sweep with mandatory performance grading
The current ngspice sweep is source-integrated. CACE remains useful proposed characterization orchestration, but changing orchestration has no measured better target result yet.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →Analog Layout. Inputs: phase3/analog/*/*.sp OR phase2/analog/*/*.sp. Outputs: phase3/analog/*/layout.mag OR phase3/analog/*/*.gds.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 5 references; destinations: vibeic_gate. Existing disposition retained.
execution_adapters_analog.py:project_population · execution_adapters_analog.py:adoption_destinations · Public facts and HARVEST destinations
Magic
Mode: direct_adapter · Source / existing records checked
This inventory did not re-run or certify this step.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
Magic
Integrated in pinned source
Policy target; not a newly deployed mode controller.
Magic PDK gencells and validated layout assembly
No LibreLane/OpenROAD transistor-level analog layout producer.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →Analog Physical Verification (per-block DRC + LVS before merge). Inputs: phase3/analog/*/layout.mag OR phase3/analog/*/*.gds. Outputs: phase3/analog/*/drc_clean.flag OR phase3/analog/*/drc.report OR phase3/analog/*/*.lyrdb OR phase3/analog/*/drc.rpt; phase3/analog/*/lvs_match.flag OR phase3/analog/*/lvs.report OR phase3/analog/*/comp.json OR phase3/analog/*/lvs.rpt.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 6 references; destinations: vibeic_gate, librelane_custom_step, drop, librelane_config. Existing disposition retained.
execution_adapters_analog.py:project_population · execution_adapters_analog.py:adoption_destinations · Public facts and HARVEST destinations
KLayout · Magic · Vibe-IC KLayout extensions
Mode: direct_adapter · Source / existing records checked
This inventory did not re-run or certify this step.
Opt-in source paths; not the production default: LibreLane · KLayout · Magic · Netgen LVS
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
Project A6 mode != direct; native default retained
LibreLane
Components: KLayout · Magic · Netgen LVS
Proposed integration
Policy target; not a newly deployed mode controller.
LibreLane physical checks on each analog block
Prefer applicable LibreLane orchestration; preserve mandatory complementary checks and uncovered intent rules.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →🔁 Post-Layout Resimulation. Inputs: phase3/analog/*/layout.mag OR phase3/analog/*/*.gds. Outputs: phase3/analog/*/pre_vs_post.json.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 6 references; destinations: drop, fork_patch:librelane, vibeic_gate. Existing disposition retained.
execution_adapters_analog.py:project_population · execution_adapters_analog.py:adoption_destinations · Public facts and HARVEST destinations
Vibe-IC program and evidence gates
Mode: program_only · Source / existing records checked
This inventory did not re-run or certify this step.
Opt-in source paths; not the production default: LibreLane · Magic · ngspice / XSPICE
Source-integrated opt-in T94 producer supersedes historical stub-only review70 description; the production default has not cut over.
Project A7 mode != direct; direct default stays skill handoff
LibreLane
Components: Magic · ngspice / XSPICE · Vibe-IC program and evidence gates
Proposed integration
Policy target; not a newly deployed mode controller.
LibreLane Magic.RCX followed by analog resimulation
Prefer applicable LibreLane orchestration; preserve mandatory complementary checks and uncovered intent rules.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →Hardmacro Generation (LEF + Liberty + GDS + Verilog). Inputs: . Outputs: phase3/analog/hardmacro/*/*.lef; phase3/analog/hardmacro/*/*.lib; phase3/analog/hardmacro/*/*.gds; phase3/analog/hardmacro/*/*.v.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 7 references; destinations: vibeic_gate, librelane_config. Existing disposition retained.
execution_adapters_analog.py:project_population · execution_adapters_analog.py:adoption_destinations · Public facts and HARVEST destinations
Magic
Mode: direct_adapter · Source / existing records checked
This inventory did not re-run or certify this step.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
LibreLane
Components: Magic · Vibe-IC program and evidence gates
Proposed integration
Policy target; not a newly deployed mode controller.
LibreLane Magic.WriteLEF with characterized macro views
Prefer applicable LibreLane orchestration; preserve mandatory complementary checks and uncovered intent rules.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →🔁 Co-Simulation (+ HW correlation when bench data exists). Inputs: . Outputs: phase3/mixed_signal/cosim/*_cosim_results.json OR phase3/mixed_signal/cosim/mixed_signal_results.json OR phase3/analog/*/hw_measurements.json.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 4 references; destinations: vibeic_gate. Existing disposition retained.
execution_adapters_analog.py:project_population · execution_adapters_analog.py:adoption_destinations · Public facts and HARVEST destinations
Vibe-IC program and evidence gates · ngspice / XSPICE · Icarus Verilog / vvp
Mode: direct_adapter · Source / existing records checked
This inventory did not re-run or certify this step.
analog_one_shot_runner.py:2504-2529 and2799 call analog_a9_cosim_emit.py. L22 scenario chooses analog ngspice or ngspice d_cosim with absolute-path Icarus libvvp; not SpiceBind.
ngspice / XSPICE
Components: Icarus Verilog / vvp · Vibe-IC program and evidence gates
Integrated in pinned source
Policy target; not a newly deployed mode controller.
Current L22-selected ngspice / d_cosim with Icarus libvvp
Use the source-integrated analog or d_cosim arm selected by the declared L22 scenario. SpiceBind remains an ultra proposed bridge; a future default override requires qualified same-input accuracy, coverage, synchronization and runtime evidence.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →Floorplan + PDN. Inputs: phase2/stage2/synth/post_dft_netlist.v; phase2/stage2/constraints/*.sdc. Outputs: phase3/stage3/pnr/floorplan.def; phase3/stage3/pnr/pdn.tcl OR phase3/stage3/pnr/pdn.done; reports/phase2/gates/stage2_compliance.json.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 13 references; destinations: librelane_config, drop, vibeic_gate, fork_patch:librelane, fork_patch:OpenROAD. Existing disposition retained.
execution_adapters_backend.py:_project_roots · execution_adapters_backend.py:adoption_paths · Public facts and HARVEST destinations
LibreLane · OpenROAD
Mode: class_scoped_librelane · Source / existing records checked
This inventory did not re-run or certify this step.
chip_pad_ring → librelane
core_only_or_hardmacro → direct
Project override and chain-coherence rules still apply.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
LibreLane
Components: OpenROAD
Integrated in pinned source
LibreLane floorplan and PDN segment
Prefer applicable LibreLane orchestration; preserve mandatory complementary checks and uncovered intent rules.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →Pad Ring (chip/IC path only). Inputs: phase3/stage3/pnr/floorplan.def; input/submission_template/tapeout_declaration.json. Outputs: phase3/stage3/pnr/padring.def; reports/phase3/padring.json; reports/phase3/pad_assignment.json; reports/phase3/io_pad_chip_top.json.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 9 references; destinations: librelane_config, vibeic_gate, fork_patch:librelane, fork_patch:OpenROAD, drop. Existing disposition retained.
execution_adapters_backend.py:_project_roots · execution_adapters_backend.py:adoption_paths · Public facts and HARVEST destinations
LibreLane · OpenROAD · Vibe-IC program and evidence gates
Mode: class_scoped_librelane · Source / existing records checked
This inventory did not re-run or certify this step.
chip_pad_ring → librelane
core_only_or_hardmacro → direct
Project override and chain-coherence rules still apply.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
LibreLane
Components: OpenROAD · Vibe-IC program and evidence gates
Integrated in pinned source
LibreLane OpenROAD.PadRing
Prefer applicable LibreLane orchestration; preserve mandatory complementary checks and uncovered intent rules.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →Clock planning. Inputs: phase3/stage3/pnr/floorplan.def; phase2/stage2/constraints/*.sdc. Outputs: phase3/stage3/cts/clock_plan.json.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 4 references; destinations: vibeic_gate, drop. Existing disposition retained.
execution_adapters_release.py:population · execution_adapters_release.py:declared_identities · Public facts and HARVEST destinations
Vibe-IC program and evidence gates
Mode: program_only · Source / existing records checked
This inventory did not re-run or certify this step.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
LibreLane
Components: OpenSTA · Vibe-IC program and evidence gates
Proposed integration
Policy target; not a newly deployed mode controller.
LibreLane/OpenSTA clock facts with declared clock planning
Prefer applicable LibreLane orchestration; preserve mandatory complementary checks and uncovered intent rules.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →Placement (global + detailed). Inputs: phase3/stage3/pnr/floorplan.def; phase3/stage3/pnr/pdn.tcl OR phase3/stage3/pnr/pdn.done. Outputs: phase3/stage3/pnr/placed.def; reports/phase3/placement_legality.json.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 5 references; destinations: drop, vibeic_gate, librelane_config. Existing disposition retained.
execution_adapters_backend.py:_project_roots · execution_adapters_backend.py:adoption_paths · Public facts and HARVEST destinations
LibreLane · OpenROAD
Mode: class_scoped_librelane · Source / existing records checked
This inventory did not re-run or certify this step.
chip_pad_ring → librelane
core_only_or_hardmacro → direct
Project override and chain-coherence rules still apply.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
LibreLane
Components: OpenROAD
Integrated in pinned source
LibreLane global and detailed placement
Prefer applicable LibreLane orchestration; preserve mandatory complementary checks and uncovered intent rules.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →Spare-cell + ECO-prep insertion (Design-for-ECO). Inputs: phase3/stage3/pnr/placed.def. Outputs: phase3/stage3/pnr/spare_cells.json; reports/spare_cell_coverage.json.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 6 references; destinations: librelane_custom_step, drop, vibeic_gate. Existing disposition retained.
execution_adapters_backend.py:_project_roots · execution_adapters_backend.py:adoption_paths · Public facts and HARVEST destinations
LibreLane · OpenROAD · Vibe-IC program and evidence gates
Mode: class_scoped_librelane · Source / existing records checked
This inventory did not re-run or certify this step.
chip_pad_ring → librelane
core_only_or_hardmacro → direct
Project override and chain-coherence rules still apply.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
LibreLane
Components: OpenROAD · Vibe-IC program and evidence gates
Integrated in pinned source
LibreLane Vibeic.InsertSpareCells with OpenROAD
Prefer applicable LibreLane orchestration; preserve mandatory complementary checks and uncovered intent rules.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →CTS (Clock Tree Synthesis). Inputs: phase3/stage3/pnr/placed.def; phase3/stage3/cts/clock_plan.json. Outputs: phase3/stage3/pnr/post_cts.def; phase3/stage3/cts/clock_tree.rpt.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 8 references; destinations: librelane_custom_step, librelane_config, vibeic_gate, drop. Existing disposition retained.
execution_adapters_backend.py:_project_roots · execution_adapters_backend.py:adoption_paths · Public facts and HARVEST destinations
LibreLane · OpenROAD
Mode: class_scoped_librelane · Source / existing records checked
This inventory did not re-run or certify this step.
chip_pad_ring → librelane
core_only_or_hardmacro → direct
Project override and chain-coherence rules still apply.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
LibreLane
Components: OpenROAD · OpenSTA
Integrated in pinned source
LibreLane OpenROAD.CTS
Prefer applicable LibreLane orchestration; preserve mandatory complementary checks and uncovered intent rules.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →🔁 Post-CTS hold fixing. Inputs: phase3/stage3/pnr/post_cts.def. Outputs: phase3/stage3/pnr/post_hold.def.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 7 references; destinations: drop, vibeic_gate. Existing disposition retained.
execution_adapters_backend.py:_project_roots · execution_adapters_backend.py:adoption_paths · Public facts and HARVEST destinations
LibreLane · OpenROAD
Mode: class_scoped_librelane · Source / existing records checked
This inventory did not re-run or certify this step.
chip_pad_ring → librelane
core_only_or_hardmacro → direct
Project override and chain-coherence rules still apply.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
LibreLane
Components: OpenROAD · OpenSTA
Integrated in pinned source
LibreLane ResizerTimingPostCTS
Prefer applicable LibreLane orchestration; preserve mandatory complementary checks and uncovered intent rules.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →Routing (global + detailed). Inputs: phase3/stage3/pnr/post_hold.def. Outputs: phase3/stage3/pnr/routed.def; phase3/stage3/pnr/openroad.log; phase3/stage3/pnr/routed.drc.rpt; reports/phase3/drc_router.rpt; reports/phase3/drc_router.json.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 11 references; destinations: fork_patch:OpenROAD, librelane_custom_step, vibeic_gate, drop, librelane_config. Existing disposition retained.
execution_adapters_backend.py:_project_roots · execution_adapters_backend.py:adoption_paths · Public facts and HARVEST destinations
LibreLane · OpenROAD · KLayout
Mode: class_scoped_librelane · Source / existing records checked
This inventory did not re-run or certify this step.
chip_pad_ring → librelane
core_only_or_hardmacro → direct
Project override and chain-coherence rules still apply.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
LibreLane
Components: OpenROAD · KLayout
Integrated in pinned source
LibreLane global/detailed routing and required checks
Prefer applicable LibreLane orchestration; preserve mandatory complementary checks and uncovered intent rules.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →Parasitic Extraction (RC → SPEF). Inputs: phase3/stage3/pnr/routed.def. Outputs: phase3/stage3/extracted/parasitic.spef OR phase3/stage3/extracted/*.spef; reports/phase2/gates/spef_extraction.json.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 8 references; destinations: librelane_custom_step, drop, fork_patch:vibeic-eda, vibeic_gate. Existing disposition retained.
execution_adapters_backend.py:_project_roots · execution_adapters_backend.py:adoption_paths · Public facts and HARVEST destinations
OpenRCX · Vibe-IC program and evidence gates
Mode: direct_adapter · Source / existing records checked
This inventory did not re-run or certify this step.
Opt-in source paths; not the production default: FasterCap
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
Opt-in fastercap_extract.py; not selected solely by installation
LibreLane
Components: OpenRCX
Proposed integration
Policy target; not a newly deployed mode controller.
LibreLane OpenROAD.RCX with calibrated rules
Prefer applicable LibreLane orchestration; preserve mandatory complementary checks and uncovered intent rules.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →🔁 Post-route timing repair pass (multi-corner repair_design + repair_timing + reroute). Inputs: . Outputs: phase3/stage3/postroute_timing_repair/repair_log.json OR phase3/stage3/postroute_timing_repair/no_repair_needed.flag; phase3/stage3/postroute_timing_repair/postroute_timing_repair_decision.json; phase3/stage3/postroute_timing_repair/postroute_timing_repair_decision.canonical.json.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 8 references; destinations: fork_patch:OpenROAD, vibeic_gate, librelane_custom_step, drop. Existing disposition retained.
execution_adapters_backend.py:_project_roots · execution_adapters_backend.py:adoption_paths · Public facts and HARVEST destinations
LibreLane · OpenROAD · Vibe-IC program and evidence gates
Mode: class_scoped_librelane · Source / existing records checked
This inventory did not re-run or certify this step.
chip_pad_ring → librelane
core_only_or_hardmacro → direct
Project override and chain-coherence rules still apply.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
LibreLane
Components: OpenROAD · Vibe-IC program and evidence gates
Integrated in pinned source
LibreLane captured post-route repair and fresh verification
Prefer applicable LibreLane orchestration; preserve mandatory complementary checks and uncovered intent rules.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →🔁 Post-route STA (multi-corner multi-mode sign-off). Inputs: phase3/stage3/extracted/parasitic.spef OR phase3/stage3/extracted/*.spef; phase2/stage2/constraints/*.sdc; phase2/stage2/constraints/pvt_matrix.json. Outputs: phase3/stage3/sta/post_route_timing.rpt; reports/phase3/sta_spef_based.rpt; reports/phase3/sta/post_route_summary.json; reports/phase3/sta/sta_corner_record_completeness.json; reports/phase3/sta/post_route_signoff_corner.json; reports/phase3/sta/architectural_residual.json.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 11 references; destinations: librelane_config, drop, vibeic_gate, fork_patch:librelane. Existing disposition retained.
execution_adapters_backend.py:_project_roots · execution_adapters_backend.py:adoption_paths · Public facts and HARVEST destinations
OpenROAD · OpenSTA
Mode: direct_adapter · Source / existing records checked
This inventory did not re-run or certify this step.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
LibreLane
Components: OpenSTA · Vibe-IC program and evidence gates
Proposed integration
Policy target; not a newly deployed mode controller.
LibreLane OpenROAD.STAPostPNR
Prefer applicable LibreLane orchestration; preserve mandatory complementary checks and uncovered intent rules.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →🔁 IR Drop (static + dynamic). Inputs: phase3/stage3/pnr/routed.def; phase3/stage3/pnr/pdn.tcl OR phase3/stage3/pnr/pdn.done. Outputs: reports/phase3/ir_drop.rpt; reports/phase3/ir_drop.json; reports/phase3/ir_drop_signoff.json; reports/phase3/dynamic_ir.json.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 8 references; destinations: fork_patch:librelane (take the max over all per-net matches and record how many nets were analysed); vibeic_gate (psm_analysis_coverage rule), librelane_custom_step (a Checker.IRDrop that compares ir__drop__worst with the declared budget), drop, drop (static); librelane_custom_step (keep inside the dynamic-IR step), librelane_custom_step (a dynamic-IR step after OpenROAD.IRDropReport) + vibeic_gate (the scaled_static_bound disclosure), fork_patch:librelane (add optional -enable_em -em_outfile to irdrop.tcl so one SDC+SPEF session produces both IR and EM), librelane_config (generate VSRC_LOC_FILES from the pad ring's supply pads on the DIE path), vibeic_gate. Existing disposition retained.
execution_adapters_backend.py:_project_roots · execution_adapters_backend.py:adoption_paths · Public facts and HARVEST destinations
OpenROAD · Vibe-IC OpenROAD fork
Mode: direct_adapter · Source / existing records checked
This inventory did not re-run or certify this step.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
LibreLane
Components: OpenROAD · Vibe-IC OpenROAD fork · Vibe-IC program and evidence gates
Proposed integration
Policy target; not a newly deployed mode controller.
LibreLane static IR plus separately bound dynamic analysis
Prefer applicable LibreLane orchestration; preserve mandatory complementary checks and uncovered intent rules.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →🔁 EM check (electromigration lifetime). Inputs: phase3/stage3/pnr/routed.def; 24. Outputs: reports/phase3/em.rpt; reports/phase3/em.json; reports/phase3/em_signoff.json; reports/phase3/em_current_authority.json.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 7 references; destinations: vibeic_gate (now); fork_patch:OpenROAD if an A/B shows check_current_density lacks per-layer LEF Jmax, vibeic_gate, fork_patch:OpenROAD (emit segment width in -em_outfile) + vibeic_gate until then, librelane_config (PDN width/pitch/supply pads chosen BEFORE routing by a PPA sweep); drop the post-route re-PnR loop, librelane_config (the PPA planner writes the supply entries into PAD_SOUTH/EAST/…), librelane_config (VSRC_LOC_FILES) + vibeic_gate (the EM verdict records its source model). Existing disposition retained.
execution_adapters_backend.py:_project_roots · execution_adapters_backend.py:adoption_paths · Public facts and HARVEST destinations
OpenROAD · Vibe-IC program and evidence gates
Mode: direct_adapter · Source / existing records checked
This inventory did not re-run or certify this step.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
Vibe-IC OpenROAD fork
Components: OpenROAD · Vibe-IC program and evidence gates
Proposed integration
Policy target; not a newly deployed mode controller.
OpenROAD fork EM geometry/current-density checks
LibreLane has no dedicated full EM step; use the proven OpenROAD fork command with complete authority.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →🔁 Antenna check (gate-oxide protection). Inputs: phase3/stage3/pnr/routed.def. Outputs: reports/phase3/antenna.rpt; reports/phase3/antenna.json; reports/phase3/antenna_signoff.json.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 7 references; destinations: vibeic_gate (antenna evidence bound to the shipped DEF/GDS digest); drop the log-scraping re-emit, drop, vibeic_gate, drop (the problem disappears with the tool path); lesson kept as vibeic_gate, fork_patch:klayout (the engine stays in vibeic/klayout gds-antenna/) + vibeic_gate (fail when OpenROAD antenna__violating__nets and klayout__antenna_error__count disagree), vibeic_gate (for any post-route ECO); drop for the tool path. Existing disposition retained.
execution_adapters_backend.py:_project_roots · execution_adapters_backend.py:adoption_paths · Public facts and HARVEST destinations
OpenROAD · Vibe-IC KLayout extensions
Mode: direct_adapter · Source / existing records checked
This inventory did not re-run or certify this step.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
LibreLane
Components: OpenROAD · KLayout · Vibe-IC program and evidence gates
Proposed integration
Policy target; not a newly deployed mode controller.
LibreLane antenna checks with qualified route/GDS evidence
Prefer applicable LibreLane orchestration; preserve mandatory complementary checks and uncovered intent rules.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →Die Finishing — seal ring + die identification (chip/IC path only). Inputs: phase3/stage3/pnr/routed.def; input/submission_template/tapeout_declaration.json. Outputs: phase3/stage3/pnr/die_finished.def OR phase3/stage3/pnr/die_finishing.SKIPPED.txt; reports/phase3/die_finishing.json.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 8 references; destinations: fork_patch:librelane (fail unless the output exists and contains new seal-ring marker geometry), fork_patch:librelane, fork_patch:librelane (interface detection; check the transposition on a non-square ihp die, NOT_MEASURED), librelane_config (macros use the Classic flow or leave KLAYOUT_SEALRING_SCRIPT unset) + vibeic_gate, librelane_config (derive the CORE/DIE margin) + vibeic_gate (refuse to seal a core in the band), drop, vibeic_gate. Existing disposition retained.
execution_adapters_backend.py:_project_roots · execution_adapters_backend.py:adoption_paths · Public facts and HARVEST destinations
KLayout
Mode: direct_adapter · Source / existing records checked
This inventory did not re-run or certify this step.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
LibreLane
Components: KLayout · Vibe-IC program and evidence gates
Proposed integration
Policy target; not a newly deployed mode controller.
LibreLane KLayout.SealRing and die finishing
Prefer applicable LibreLane orchestration; preserve mandatory complementary checks and uncovered intent rules.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →🔁 Signal Integrity (Crosstalk / Noise / Glitch + MCF crosstalk-delay). Inputs: phase3/stage3/extracted/parasitic.spef OR phase3/stage3/extracted/*.spef. Outputs: reports/phase3/si_crosstalk.rpt OR reports/phase3/si_crosstalk.json; reports/phase3/si_mcf_sta.json; reports/phase3/si_mcf_sta.rpt.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 7 references; destinations: fork_patch:OpenROAD, vibeic_gate, drop. Existing disposition retained.
execution_adapters_backend.py:_project_roots · execution_adapters_backend.py:adoption_paths · Public facts and HARVEST destinations
OpenSTA · Vibe-IC OpenROAD fork
Mode: direct_adapter · Source / existing records checked
This inventory did not re-run or certify this step.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
Vibe-IC OpenSTA fork
Components: Vibe-IC OpenROAD fork · Vibe-IC program and evidence gates
Proposed integration
Policy target; not a newly deployed mode controller.
Fork SI kernels with timing-bound crosstalk/noise evidence
No complete native LibreLane SI signoff step.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →🔁 PERC / Reliability sign-off (ESD + latch-up + cross-domain). Inputs: phase3/stage3/pnr/routed.def. Outputs: reports/phase3/perc_equivalent.json; reports/phase3/perc_equivalent.rpt; reports/phase3/PERC_SIGNOFF_MEMO.md; reports/phase2/gates/perc_signoff.json.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 7 references; destinations: vibeic_gate, librelane_config (read FP_TAPCELL_DIST) + vibeic_gate (screen radius = pitch/2). Existing disposition retained.
execution_adapters_backend.py:_project_roots · execution_adapters_backend.py:adoption_paths · Public facts and HARVEST destinations
KLayout · Vibe-IC program and evidence gates
Mode: direct_adapter · Source / existing records checked
This inventory did not re-run or certify this step.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
Vibe-IC program and evidence gates
Components: KLayout
Integrated in pinned source
Policy target; not a newly deployed mode controller.
Declared ESD/latch-up screen with measured topology/geometry
No LibreLane/OpenROAD full PERC engine; own bounded evidence grader remains.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →Post-Layout Gate-Level Simulation (Post-Sim + SDF). Inputs: phase2/stage2/synth/post_dft_netlist.v. Outputs: phase3/stage3/sim_postlayout/results.log OR phase3/stage3/sim_postlayout/pass.flag; reports/phase2/gates/post_layout_sim.json.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 6 references; destinations: drop, vibeic_gate, librelane_custom_step, fork_patch:iverilog. Existing disposition retained.
execution_adapters_backend.py:_project_roots · execution_adapters_backend.py:adoption_paths · Public facts and HARVEST destinations
OpenSTA · Icarus Verilog / vvp
Mode: direct_adapter · Source / existing records checked
This inventory did not re-run or certify this step.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
Icarus Verilog / vvp
Components: OpenSTA · Vibe-IC program and evidence gates
Integrated in pinned source
Policy target; not a newly deployed mode controller.
Icarus post-layout simulation with applied SDF
LibreLane has no complete SDF simulation executor.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →Post-Layout SPICE Verification (critical-path correlation + analog). Inputs: the PDK device models / tech decks (PDK_ROOT — outside the project tree). Outputs: phase3/stage3/spice/*.sp OR phase3/stage3/spice/*.spice OR sim_spice/*.sp; phase3/stage3/spice/correlation.json OR reports/phase3/spice_correlation.json.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 8 references; destinations: drop, vibeic_gate, librelane_custom_step. Existing disposition retained.
execution_adapters_backend.py:_project_roots · execution_adapters_backend.py:adoption_paths · Public facts and HARVEST destinations
ngspice / XSPICE · OpenSTA
Mode: direct_adapter · Source / existing records checked
This inventory did not re-run or certify this step.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
OpenSTA
Components: ngspice / XSPICE · Vibe-IC program and evidence gates
Proposed integration
Policy target; not a newly deployed mode controller.
OpenSTA path-SPICE export with circuit simulation
LibreLane supplies partial extraction only; OpenSTA owns path export.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →Power analysis (pre/post-layout). Inputs: phase3/stage3/extracted/parasitic.spef OR phase3/stage3/extracted/*.spef. Outputs: reports/phase3/power.rpt; reports/phase3/power.json.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 5 references; destinations: drop (take sign-off power from STAPostPNR); keep the lesson as vibeic_gate (a power record names the netlist it linked), vibeic_gate (+ fork_patch:librelane: optional SAIF/VCD read and a power__activity_basis / annotated-count metric), vibeic_gate, drop, librelane_custom_step (use OpenROAD read_upf as the check). Existing disposition retained.
execution_adapters_backend.py:_project_roots · execution_adapters_backend.py:adoption_paths · Public facts and HARVEST destinations
OpenSTA
Mode: direct_adapter · Source / existing records checked
This inventory did not re-run or certify this step.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
LibreLane
Components: OpenSTA · Vibe-IC program and evidence gates
Proposed integration
Policy target; not a newly deployed mode controller.
LibreLane STAPostPNR per-corner power metrics
Prefer applicable LibreLane orchestration; preserve mandatory complementary checks and uncovered intent rules.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →Metal Fill (ECO-aware density fill insertion). Inputs: phase3/stage3/pnr/routed.def; phase3/stage3/pnr/spare_cells.json. Outputs: phase3/stage3/pnr/filled.def OR phase3/stage3/pnr/metal_fill.done; reports/density.json OR reports/phase3/density.json; reports/density.rpt OR reports/phase3/density.rpt.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 9 references; destinations: fork_patch:OpenROAD (a region/density-cap option for filler_placement) or fork_patch:librelane (an optional fill region), vibeic_gate (read LibreLane's DPL filler count and the odb row utilisation), drop (keep the ordering lesson), drop, fork_patch:klayout (the engine stays as a second arm) + vibeic_gate (UNREACHABLE_BY_ANY_FILL refusal), fork_patch:klayout, vibeic_gate. Existing disposition retained.
execution_adapters_backend.py:_project_roots · execution_adapters_backend.py:adoption_paths · Public facts and HARVEST destinations
OpenROAD · KLayout · Vibe-IC KLayout extensions
Mode: direct_adapter · Source / existing records checked
This inventory did not re-run or certify this step.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
LibreLane
Components: OpenROAD · KLayout · Vibe-IC program and evidence gates
Proposed integration
Policy target; not a newly deployed mode controller.
LibreLane fill insertion and final density verification
Prefer applicable LibreLane orchestration; preserve mandatory complementary checks and uncovered intent rules.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →DFM screen (CMP density + redundant-via ratio + foundry-side OPC/RET disclosure). Inputs: 34. Outputs: reports/phase3/dfm_screen.json.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 6 references; destinations: vibeic_gate, drop. Existing disposition retained.
execution_adapters_release.py:population · execution_adapters_release.py:declared_identities · Public facts and HARVEST destinations
Vibe-IC program and evidence gates
Mode: program_only · Source / existing records checked
This inventory did not re-run or certify this step.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
LibreLane
Components: KLayout · Vibe-IC program and evidence gates
Proposed integration
Policy target; not a newly deployed mode controller.
LibreLane density/manufacturability metrics with DFM audit
Prefer applicable LibreLane orchestration; preserve mandatory complementary checks and uncovered intent rules.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →GDSII output (after routed-layout pre-stream admission). Inputs: phase3/stage3/pnr/filled.def OR phase3/stage3/pnr/metal_fill.done. Outputs: phase3/stage4/gds/*.gds; phase3/stage3/pnr/*stream_out.log; phase3/stage3/pnr/*.stream_inputs.json; phase3/stage3/pnr/magic_stream_out.tcl OR phase3/stage3/pnr/stream_out.py; reports/phase3/pad_ring_route_evidence.json; reports/phase3/gates/stage3_compliance.json; reports/phase3/layout_receipts.json.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 11 references; destinations: vibeic_gate (also fork_patch:librelane: an element-count checker after Magic.StreamOut), vibeic_gate, drop, librelane_custom_step (run Magic.DRC+KLayout.DRC on MAG_GDS and KLAYOUT_GDS, promote the cleaner one) fed to the PPA layer, fork_patch:librelane (use x1-x0/y1-y0; verify the ihp width/height order), drop (keep a vibeic_gate: no step writes under input/), librelane_custom_step (non-deferred checker set before Magic.StreamOut). Existing disposition retained.
execution_adapters_backend.py:_project_roots · execution_adapters_backend.py:adoption_paths · Public facts and HARVEST destinations
Magic · KLayout · Vibe-IC program and evidence gates
Mode: direct_adapter · Source / existing records checked
This inventory did not re-run or certify this step.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
LibreLane
Components: KLayout · Vibe-IC program and evidence gates
Proposed integration
Policy target; not a newly deployed mode controller.
LibreLane stream-out with macro and finishing views
Prefer applicable LibreLane orchestration; preserve mandatory complementary checks and uncovered intent rules.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →GDS stream-out / finishing fidelity — the shipped GDS XOR'd against this run's own pre-finishing boundary. Inputs: . Outputs: reports/phase3/gds_xor.json.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 7 references; destinations: librelane_custom_step (a Checker after KLayout.Filler that runs xor.drc between the pre-SealRing GDS state and the final GDS, with KLAYOUT_XOR_IGNORE_LAYERS = layers the SealRing/Filler steps added), fork_patch:librelane (print a per-layout cell/shape census in xor.drc) + vibeic_gate, fork_patch:librelane (missing metric under RUN_KLAYOUT_XOR=true is an error), vibeic_gate, drop, librelane_config (KLAYOUT_XOR_IGNORE_LAYERS). Existing disposition retained.
execution_adapters_backend.py:_project_roots · execution_adapters_backend.py:adoption_paths · Public facts and HARVEST destinations
KLayout
Mode: direct_adapter · Source / existing records checked
This inventory did not re-run or certify this step.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
LibreLane
Components: KLayout · Vibe-IC program and evidence gates
Proposed integration
Policy target; not a newly deployed mode controller.
LibreLane KLayout.XOR with an authoritative per-run boundary
Prefer applicable LibreLane orchestration; preserve mandatory complementary checks and uncovered intent rules.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →🔁 Physical Verification (DRC + LVS + ERC + Density). Inputs: phase3/stage3/pnr/routed.def. Outputs: reports/phase3/drc_signoff.rpt; reports/phase3/lvs.rpt; reports/phase3/erc.rpt; reports/phase3/lvs.json; reports/phase2/gates/erc_density.json; reports/phase3/magic_illegal_overlap.json; reports/phase3/lvs_verdict.json; reports/phase3/drc_signoff.json; reports/phase3/perc_sweep.json.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 12 references; destinations: fork_patch:librelane (a missing metric under RUN_*=true is an error) + vibeic_gate, drop (waivers must be explicit human waivers, e.g. waiver_growth_check), drop (keep signoff_drc_format.classify_file as a vibeic_gate), vibeic_gate (wrap LibreLane step invocation in the progress supervisor), vibeic_gate (region clustering over LibreLane feedback.xml), librelane_custom_step (KLayout.SVRFDRC wrapping the fork engine); engine stays fork_patch:klayout, librelane_config, vibeic_gate (classifier over the Netgen JSON report), librelane_custom_step, vibeic_gate. Existing disposition retained.
execution_adapters_backend.py:_project_roots · execution_adapters_backend.py:adoption_paths · Public facts and HARVEST destinations
KLayout · Magic · Netgen LVS · Vibe-IC KLayout extensions
Mode: direct_adapter · Source / existing records checked
This inventory did not re-run or certify this step.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
LibreLane
Components: KLayout · Magic · Netgen LVS · Vibe-IC program and evidence gates
Proposed integration
Policy target; not a newly deployed mode controller.
LibreLane final physical-verification suite
Prefer applicable LibreLane orchestration; preserve mandatory complementary checks and uncovered intent rules.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →Tapeout checklist (final sign-off confirmation). Inputs: . Outputs: reports/audit/tapeout_checklist.json.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 4 references; destinations: vibeic_gate, fork_patch:librelane (N/A for an enabled RUN_* engine is a failure). Existing disposition retained.
execution_adapters_release.py:population · execution_adapters_release.py:declared_identities · Public facts and HARVEST destinations
Vibe-IC program and evidence gates
Mode: program_only · Source / existing records checked
This inventory did not re-run or certify this step.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
Vibe-IC program and evidence gates
Components: LibreLane
Integrated in pinned source
Policy target; not a newly deployed mode controller.
Release checklist over measured signoff receipts
No EDA engine determines every project/operator release contract.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →Sign-off metrics aggregation — the run's own checker verdicts, under the names the release documents read. Inputs: phase3/stage4/gds/*.gds. Outputs: phase3/final/metrics.json; reports/phase3/signoff_metrics_aggregate.json.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 5 references; destinations: fork_patch:librelane (emit an explicit NOT_MEASURED marker for enabled-but-unrun metric producers), vibeic_gate, drop. Existing disposition retained.
execution_adapters_release.py:population · execution_adapters_release.py:declared_identities · Public facts and HARVEST destinations
Vibe-IC program and evidence gates
Mode: program_only · Source / existing records checked
This inventory did not re-run or certify this step.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
LibreLane
Components: Vibe-IC program and evidence gates
Proposed integration
Policy target; not a newly deployed mode controller.
LibreLane State metrics with source-bound aggregation
Prefer applicable LibreLane orchestration; preserve mandatory complementary checks and uncovered intent rules.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →Digital Hardmacro Generation — LEF + Liberty + GDS + Verilog (delivered on EVERY route). Inputs: phase3/stage4/gds/*.gds. Outputs: phase3/stage4/hardmacro/*.lef; phase3/stage4/hardmacro/*.lib; phase3/stage4/hardmacro/*.gds; phase3/stage4/hardmacro/*.v; reports/phase3/digital_hardmacro.json; phase3/stage4/documentation/ip/*/IP_DATASHEET.md; phase3/stage4/documentation/ip/*/IP_INTEGRATION_GUIDE.md; phase3/stage4/documentation/ip/*/RELEASE_NOTES.md; phase3/stage4/documentation/ip/*/ERRATA.md; phase3/stage4/documentation/ip/*/DELIVERABLES_MANIFEST.md; phase3/stage4/documentation/ip/*/documentation_manifest.yaml.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 6 references; destinations: fork_patch:OpenSTA (option to emit pg_pin from design power nets), drop (use the per-corner libs; keep the 'never characterise from pre-route' rule as a vibeic_gate), drop (keep 'each PIN once, with DIRECTION/USE' as a vibeic_gate in digital_hardmacro_check), librelane_config, vibeic_gate. Existing disposition retained.
execution_adapters_release.py:population · execution_adapters_release.py:declared_identities · Public facts and HARVEST destinations
Magic · OpenROAD · OpenSTA · Vibe-IC program and evidence gates
Mode: direct_adapter · Source / existing records checked
This inventory did not re-run or certify this step.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
LibreLane
Components: Magic · OpenSTA · Vibe-IC program and evidence gates
Proposed integration
Policy target; not a newly deployed mode controller.
LibreLane LEF/header/per-corner timing macro views
Prefer applicable LibreLane orchestration; preserve mandatory complementary checks and uncovered intent rules.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →Tape-out Precheck — our general ladder, plus the operator's own refusal where the PDK ships one (chip/IC path only). Inputs: phase3/stage4/gds/*.gds; input/submission_template/tapeout_declaration.json. Outputs: reports/phase3/tapeout_precheck.json; reports/phase3/general_precheck.json; reports/phase3/shuttle_precheck.json; reports/phase3/docs/SIGNOFF_*.html; reports/phase3/docs/BRIEF_*.html; phase3/stage4/documentation/ic/*/PRELIMINARY_DATASHEET.md; phase3/stage4/documentation/ic/*/RELEASE_NOTES.md; phase3/stage4/documentation/ic/*/ERRATA.md; phase3/stage4/documentation/ic/*/documentation_manifest.yaml.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 6 references; destinations: vibeic_gate, librelane_custom_step, drop the marker writer after migrating 31/37; keep the disclosure rung as a vibeic_gate, vibeic_gate (keep; host-runnable). Existing disposition retained.
execution_adapters_release.py:population · execution_adapters_release.py:declared_identities · Public facts and HARVEST destinations
Submission operator precheck · Vibe-IC program and evidence gates
Mode: direct_adapter · Source / existing records checked
This inventory did not re-run or certify this step.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
Submission operator precheck
Components: Vibe-IC program and evidence gates
Integrated in pinned source
Policy target; not a newly deployed mode controller.
Operator precheck plus general evidence ladder
The operator owns its submission checks; LibreLane checks are prerequisites.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →Foundry Handoff (mask spec + WAT plan + scribe layout + corner test kit). Inputs: phase3/stage4/gds/*.gds. Outputs: phase3/stage4/foundry_handoff/mask_spec.json; phase3/stage4/foundry_handoff/wat_plan.json; phase3/stage4/foundry_handoff/scribe_line_layout.gds OR phase3/stage4/foundry_handoff/scribe_line_layout.PENDING_FOUNDRY.txt; phase3/stage4/foundry_handoff/corner_test_vectors.json.
Declared physical handoff requires applicable external evidence; software source is not physical completion.
Original HARVEST: 4 references; destinations: vibeic_gate, vibeic_gate (keep the refusal), drop the cause. Existing disposition retained.
execution_adapters_release.py:population · execution_adapters_release.py:declared_identities · Public facts and HARVEST destinations
Vibe-IC program and evidence gates
Mode: program_only · Source / existing records checked
This inventory did not re-run or certify this step.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
Vibe-IC program and evidence gates
Components: KLayout
Integrated in pinned source
Policy target; not a newly deployed mode controller.
Foundry/operator handoff package and authority audit
No complete existing software producer covers the operator-specific package.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →FPGA final sign-off (recompile + on-board test). Inputs: phase2/stage1/rtl/*.sv OR phase2/stage1/rtl/*.v; a physical FPGA board on the bench. Outputs: phase2/stage1/fpga/final/*.sof; reports/phase2/fpga/on_board_pass.json.
Declared physical handoff requires applicable external evidence; software source is not physical completion.
Original HARVEST: 2 references; destinations: vibeic_gate. Existing disposition retained.
execution_adapters_release.py:population · execution_adapters_release.py:declared_identities · Public facts and HARVEST destinations
Quartus Prime
Mode: direct_adapter · Source / existing records checked
This inventory did not re-run or certify this step.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
Quartus Prime
Components: Vibe-IC program and evidence gates
Tool / adapter needed
Policy target; not a newly deployed mode controller.
FPGA recompile/program plus on-board attestation
No LibreLane/OpenROAD FPGA execution path.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →Fabrication (foundry mask-set + wafer fab — external). Inputs: 38. Outputs: phase3/stage5_manufacturing/mask_set_received.json; phase3/stage5_manufacturing/wafer_lot_received.json.
Declared physical handoff requires applicable external evidence; software source is not physical completion.
Original HARVEST: 3 references; destinations: vibeic_gate. Existing disposition retained.
execution_adapters_release.py:population · execution_adapters_release.py:declared_identities · Public facts and HARVEST destinations
Vibe-IC program and evidence gates
Mode: external_attestation · Source / existing records checked
This inventory did not re-run or certify this step.
Validator reads fabrication attestation; no physical fabrication is performed by the program.
External wafer fabrication service
Components: Vibe-IC program and evidence gates
External physical process
Policy target; not a newly deployed mode controller.
External fabrication with lot/wafer attestation
This is a physical external process.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →Wafer Sort / Probe Test (ATE + probe card). Inputs: phase3/stage5_manufacturing/wafer_lot_received.json. Outputs: phase3/stage5_manufacturing/wafer_sort_yield.json; phase3/stage5_manufacturing/wafer_map.csv.
Declared physical handoff requires applicable external evidence; software source is not physical completion.
Original HARVEST: 2 references; destinations: vibeic_gate. Existing disposition retained.
execution_adapters_release.py:population · execution_adapters_release.py:declared_identities · Public facts and HARVEST destinations
Vibe-IC program and evidence gates
Mode: external_attestation · Source / existing records checked
This inventory did not re-run or certify this step.
Validator reads declared wafer-probe/test evidence; no ATE execution is implied.
NI STS / PXI ATE
Components: Vibe-IC program and evidence gates
License / equipment required
Policy target; not a newly deployed mode controller.
External calibrated wafer probe and ATE
Physical production test, not an EDA flow.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →Packaging (assembly: wirebond / FC-CSP / WLCSP). Inputs: 41. Outputs: phase3/stage5_manufacturing/packaging_log.json.
Declared physical handoff requires applicable external evidence; software source is not physical completion.
Original HARVEST: 2 references; destinations: vibeic_gate. Existing disposition retained.
execution_adapters_release.py:population · execution_adapters_release.py:declared_identities · Public facts and HARVEST destinations
Vibe-IC program and evidence gates
Mode: external_attestation · Source / existing records checked
This inventory did not re-run or certify this step.
Validator reads packaging evidence; no assembly process is performed locally.
External die/package assembly service
Components: Vibe-IC program and evidence gates
External physical process
Policy target; not a newly deployed mode controller.
External assembly with package-specific attestations
This is a physical external process.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →Final Test (ATE: functional + parametric + burn-in). Inputs: phase3/stage5_manufacturing/packaging_log.json. Outputs: phase3/stage5_manufacturing/final_test_yield.json; phase3/stage5_manufacturing/burn_in_results.json.
Declared physical handoff requires applicable external evidence; software source is not physical completion.
Original HARVEST: 1 references; destinations: vibeic_gate. Existing disposition retained.
execution_adapters_release.py:population · execution_adapters_release.py:declared_identities · Public facts and HARVEST destinations
Vibe-IC program and evidence gates
Mode: external_attestation · Source / existing records checked
This inventory did not re-run or certify this step.
Validator reads package/final-test evidence; no ATE execution is implied.
NI STS / PXI ATE
Components: Vibe-IC program and evidence gates
License / equipment required
Policy target; not a newly deployed mode controller.
External final ATE and declared burn-in
Physical production test, not an EDA flow.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →Reliability qualification (HTOL / FIT attestation). Inputs: 43. Outputs: phase3/stage5_manufacturing/htol_results.json.
Declared physical handoff requires applicable external evidence; software source is not physical completion.
Original HARVEST: 4 references; destinations: vibeic_gate. Existing disposition retained.
execution_adapters_release.py:population · execution_adapters_release.py:declared_identities · Public facts and HARVEST destinations
Vibe-IC program and evidence gates
Mode: external_attestation · Source / existing records checked
This inventory did not re-run or certify this step.
Validator reads reliability evidence; no physical stress or qualification run is performed locally.
Physical reliability qualification lab
Components: Vibe-IC program and evidence gates
External physical process
Policy target; not a newly deployed mode controller.
External qualification with measured stress and FIT evidence
This is a physical external process.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →Mixed-Signal Top-Level Integration (A+D GDS merge + macro placement). Inputs: phase3/stage4/gds/*.gds; A8. Outputs: phase3/mixed_signal/top_merged.gds; reports/analog/mixed_signal/merge.json.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 10 references; destinations: vibeic_gate, drop, librelane_config. Existing disposition retained.
execution_adapters_analog.py:project_population · execution_adapters_analog.py:adoption_destinations · Public facts and HARVEST destinations
KLayout · Magic · Netgen LVS
Mode: direct_adapter · Source / existing records checked
This inventory did not re-run or certify this step.
Current route merges with KLayout, extracts with Magic and checks with Netgen. OpenROAD placement is an applicable proposed component, not inferred current execution.
LibreLane
Components: OpenROAD · KLayout · Magic · Netgen LVS · Vibe-IC program and evidence gates
Proposed integration
Policy target; not a newly deployed mode controller.
LibreLane macro placement and mixed-signal stream integration
Prefer applicable LibreLane orchestration; preserve mandatory complementary checks and uncovered intent rules.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →Mixed-Signal Power Domain + Level Shifter / Isolation Verification. Inputs: phase3/mixed_signal/top_merged.gds. Outputs: reports/analog/mixed_signal/power_domain.json; reports/analog/mixed_signal/level_shifter.json; reports/analog/mixed_signal/isolation.json.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 6 references; destinations: vibeic_gate, librelane_custom_step. Existing disposition retained.
execution_adapters_analog.py:project_population · execution_adapters_analog.py:adoption_destinations · Public facts and HARVEST destinations
Vibe-IC program and evidence gates
Mode: program_only · Source / existing records checked
This inventory did not re-run or certify this step.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
OpenROAD
Components: Vibe-IC program and evidence gates
Proposed integration
Policy target; not a newly deployed mode controller.
OpenROAD UPF representation with domain/crossing checks
Use OpenROAD partial power-intent support; retain uncovered rules as program checks.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →Mixed-Signal Verification (AMS co-sim + RNM + interface signal integrity). Inputs: phase3/mixed_signal/top_merged.gds. Outputs: phase3/mixed_signal/cosim/mixed_signal_results.json; reports/analog/mixed_signal/interface_si.json.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 5 references; destinations: vibeic_gate, librelane_custom_step. Existing disposition retained.
execution_adapters_analog.py:project_population · execution_adapters_analog.py:adoption_destinations · Public facts and HARVEST destinations
Vibe-IC program and evidence gates
Mode: program_only · Source / existing records checked
This inventory did not re-run or certify this step.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
Vibe-IC program and evidence gates
Components: ngspice / XSPICE · Icarus Verilog / vvp
Proposed integration
Policy target; not a newly deployed mode controller.
Current interface-evidence grader; reuse proven A9 solver where applicable
No current complete M3 interface producer is integrated. Retain the existing grader; proposed reuse of the source-integrated A9 ngspice/d_cosim solver must satisfy M3 interface contracts. cocotbext-ams and SpiceBind are future adapters, not proven better defaults.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →Mixed-Signal Sign-Off (top-level PV + final verdict). Inputs: phase3/mixed_signal/top_merged.gds. Outputs: reports/analog/mixed_signal/signoff.json.
No physical handoff is declared for this row; qualification still requires applicable current evidence.
Original HARVEST: 5 references; destinations: vibeic_gate, librelane_config. Existing disposition retained.
execution_adapters_analog.py:project_population · execution_adapters_analog.py:adoption_destinations · Public facts and HARVEST destinations
Vibe-IC program and evidence gates
Mode: program_only · Source / existing records checked
This inventory did not re-run or certify this step.
Current adapter classification follows actual calls in the cited corrected source review and pinned source; tool presence is not the integration criterion.
LibreLane
Components: KLayout · Magic · Netgen LVS · Vibe-IC program and evidence gates
Proposed integration
Policy target; not a newly deployed mode controller.
LibreLane top-level PV with mixed-signal completeness audit
Prefer applicable LibreLane orchestration; preserve mandatory complementary checks and uncovered intent rules.
Pinned source: f88175263 ↗
Inputs, outputs and nine gates →No matching steps. Try another tool, phase or status.
Current release: 13 chip_pad_ring class defaults (12 LibreLane, Step 8 dual), subject to prerequisites and overrides. The catalog cards retain the reviewed v1.26.79 snapshot; the new default / ultra controller is unreleased.
Reviewed catalog v1.26.79 · 70 steps / 63 tools / 333 recommendation paths: 2026-09-30T02:49:04.051220+08:00 · f88175263 ↗ · Source and historical records only; no fresh runtime or IC sign-off is claimed. Detailed technical notes are retained in their original English. · Download the snapshot
Each row separates EDA tools from our programs, lists declared inputs and outputs, and shows nine evidence states. Hover or focus a gate chip for its source note. “Missing” includes unmeasured and not derivable from source; it is never zero or PASS. Corrected on 2026-09-25 against vibe-ic commit 40cc2c66d, applying the verified findings of the adversarial review at the end of this page: 324 cell edits, each proposed from source and then challenged by an independent skeptic. D9 cells are now derived from the plugin's own D9 ledger test with its disclosed stand-ins.
| Step | EDA | Programs | Inputs → outputs | D1 | D2 | D3 | D4 | D5 | D6 | D7 | D8 | D9 | AI role |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Document extraction | |||||||||||||
| D1 Phase 1 Doc Extraction (17 skills + dialogue entry → L1-L27) | — | 36 programsanalog_a0_skip_forbidden_check.py constants_validation.py cross_layer_reference_check.py extraction_credited_by_prose_only_check.py input_docs_coverage_check.py integration_spec_audit.py l10_test_case_oracle_anchor_check.py l11_otp_content_consumer_contract_check.py l12_sequences_in_consumed_layer_check.py l13_bringup_contract_check.py l14_protocol_versioning_contract_check.py l15_encoding_tables_contract_check.py l16_compliance_properties_actionable_check.py l17_channel_catalog_consumer_contract_check.py l18_interconnect_topology_factuality_check.py l21_macro_supply_rail_declared_check.py l22_analog_verification_plan_emit.py l6_fsm_scaffold_actionable_check.py l7_debug_access_grounding_check.py l8_clock_period_actionability_check.py l8_sta_clock_period_design_owned_check.py l9_floorplan_contract_check.py l_doc_cross_consistency_check.py l_doc_parity_diff.py l_doc_todo_stub_count_check.py oracle_vector_gen.py phase1_all_l_docs_present_check.py phase1_coverage_report_present_check.py phase1_expert_parse_track.py phase1_expert_track_evidence_check.py phase1_planned_consumer_starved_check.py phase1_provenance_presence_check.py spec_review_lint.py phase1_one_shot_runner.py phase1_doc_one_shot_runner.py tools/phase1_engine/cli.py | Inputs and outputsIN phase1/input_prompt/* OR phase1/input_doc/* OR input/docs/* OR input/phase1_prompt.md OR input/phase1_structured.yaml OUT phase1/generated_docs/L1_DATASHEET.json phase1/generated_docs/L2_FRS.json phase1/generated_docs/L3_CMD_PROTOCOL.json phase1/generated_docs/L4_REGMAP.json phase1/generated_docs/L5_ADI_SPEC.json phase1/generated_docs/L6_CONTROL_LOGIC.json phase1/generated_docs/L7_TEST_DEBUG.json phase1/generated_docs/L8_TIMING_WAVEFORM.json phase1/generated_docs/L8_RTL_CONSTANTS.json phase1/generated_docs/L9_INTEGRATION_SPEC.json phase1/generated_docs/L10_TEST_CASES.json phase1/generated_docs/L11_OTP_CONTENT.json phase1/generated_docs/L12_BEHAVIORAL_SEQUENCES.json phase1/generated_docs/L13_*.json phase1/generated_docs/L19_CONSTRAINTS_PDK.json phase1/generated_docs/L21_POWER_INTENT.json reports/phase1/extraction_coverage_report.md reports/phase1/extraction_coverage_report.json reports/audit/phase1/expert_parse_track.json phase1/extraction_patterns.json phase1/generated_docs/L22_VERIFICATION_PLAN.json phase1/generated_docs/L14_PROTOCOL_VERSIONING.json (produced, undeclared) phase1/generated_docs/L15_ENCODING_TABLES.json (produced, undeclared) phase1/generated_docs/L16_COMPLIANCE_PROPERTIES.json (produced, undeclared) phase1/generated_docs/L17_CHANNEL_SIGNAL_CATALOG.json (produced, undeclared) phase1/generated_docs/L18_INTERCONNECT_TOPOLOGY.json (produced, undeclared) phase1/generated_docs/L20_DFT_SCAN_TOPOLOGY.json (produced, undeclared) phase1/generated_docs/L23_SECURITY_REQUIREMENTS.json (produced, undeclared) phase1/generated_docs/L24_SIGNOFF.json (produced, undeclared) phase1/generated_docs/L25_RELIABILITY_MISSION_PROFILE.json (produced, undeclared) phase1/generated_docs/L26_MECHANICAL_TRANSDUCTION.json (produced, undeclared) phase1/generated_docs/L27_MEMORY_MODULE_SPD.json (produced, undeclared) phase1/human_docs/L*.md (produced, undeclared) | done | done | missing | missing | done | done | missing | done | partial | before + afterAI interprets design input before L-doc extraction and checks that key extracted facts match source intent; every design. |
| 0.5ic Submission Template Ingest — the operator's slot geometry and fixtures (chip/IC path only) | klayout | 6 programssubmission_template_answers.py submission_template_check.py submission_template_fetch.py submission_template_ingest.py tapeout_declaration_check.py tapeout_declaration_gen.py | Inputs and outputsIN unknown (external input path undeclared: the shuttle operator's published project template — the repository or archive that pins the slot geometry, ships the die-identification fixtures, and lists the pads for each slot. Declared as external and unprobed because it is fetched, not produced, and the flow must be able to say it was never fetched.) OUT input/submission_template/slots/*.yaml OR input/submission_template/NO_TEMPLATE.txt OR input/submission_template/SELF_TAPEOUT.txt reports/phase1/submission_template.json input/submission_template/tapeout_declaration.json reports/phase1/tapeout_declaration.json input/submission_template_source/* (produced, undeclared) reports/phase1/submission_template_fetch.json (produced, undeclared) input/submission_template/operator_answers.json (produced, undeclared) reports/phase1/submission_template_answers.json (produced, undeclared) | done | done | missing | missing | done | done | missing | done | partial | noneProgram-owned step; apply declared gates and completion auditor. |
| Step | EDA | Programs | Inputs → outputs | D1 | D2 | D3 | D4 | D5 | D6 | D7 | D8 | D9 | AI role |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RTL generation and verification | |||||||||||||
| 1 Spec-to-RTL | iverilog | 13 programsarith_declaration_emit.py ip_catalog_pull.py staged_rtl_reused_ip_manifest_emit.py flow_step_output_content_check.py design_one_shot_runner.py::step_rtl_gen aid_class_rtl_gen.py data_converter_rtl_gen.py rtl_hygiene_lint.py design_one_shot_runner.py::step_reused_ip_consume leaf_typo_alias_emit.py reset_clock_variant_alias.py design_one_shot_runner.py::step_arith_declaration_emit spec_declaration_emit.py | Inputs and outputsOUT phase2/stage1/rtl/*.sv OR phase2/stage1/rtl/*.v phase2/stage1/rtl/SOURCE_MANIFEST.json plugin_output/declaration.json phase2/stage1/rtl.provenance.json (produced, undeclared) phase2/stage1/fallback_skill.md (produced, undeclared) | done | done | missing | missing | done | done | missing | done | partial | before + afterOnly on RTL generator waiver: AI authors/configures RTL, then reviews its behavior against L-docs. |
| 2 🔁 RTL validation (rewrite fidelity + lint + Quartus-unsafe patterns + RTL-bug claim schema) | iverilog | 29 programsarith_ss_corner_risk_check.py counter_decode_lookahead_phase_check.py crosslayer_rewrite_equivalence.py (declared, not run) crosslayer_rewrite_equivalence_check.py crosslayer_search_space.py flow_compliance_check.py fpga_wrapper_input_polluter_check.py fresh_agent_rtl_bug_density_metric.py internal_vs_external_timing_check.py l9_submodule_conformance_check.py memory_read_pipeline_check.py nba_addr_read_race_check.py periodic_timer_vs_rx_activity_check.py rom_init_lint.py rsp_example_otp_consistency_check.py rtl_bug_report_schema_check.py rtl_hygiene_lint.py slot_pad_budget_check.py spec_conformance_check.py spec_response_delay_check.py stage_on_pass_review.py threshold_range_contiguity_check.py clock_divider_phase_form_check.py clock_divider_ratio_oracle_check.py edge_history_reset_phantom_check.py ramp_waveform_oracle_check.py worked_example_sequence_oracle_check.py design_one_shot_runner.py::step_determinism_gates design_one_shot_runner.py::step_emit_phase2_manifests | Inputs and outputsOUT reports/phase2/lint/rtl_hygiene.json reports/phase2/lint/rom_init_lint.json reports/crosslayer/rewrite_equivalence_check.json reports/phase2/gates/slot_pad_budget.json | done | done | missing | missing | done | done | missing | done | partial | noneProgram-owned step; apply declared gates and completion auditor. |
| 3 🔁 CDC / RDC check | — | 5 programscdc_async_input_check.py cdc_crossing_check.py clock_domain_reg_crossing_check.py reset_dependency_check.py design_one_shot_runner.py::step_emit_phase2_manifests | Inputs and outputsIN phase2/stage1/rtl/*.sv OR phase2/stage1/rtl/*.v OUT reports/phase2/cdc/crossing.json reports/phase2/cdc/async_input.json reports/phase2/cdc/reset_dep.json | done | done | missing | missing | done | done | missing | done | partial | noneProgram-owned step; apply declared gates and completion auditor. |
| 4 🔁 Simulation (testbench-based + L10/L12 coverage + Verilator coverage) | iverilog sv2v verilator | 16 programsbehavioral_evidence_per_spec_item_check.py coverage_closure.py cpu_functional_oracle_waiver_check.py dispatcher_awake_gate_check.py functional_state_transition_coverage_check.py l10_tb_conformance_check.py l12_tb_coverage_check.py professional_tb_check.py professional_tb_gen.py protocol_turnaround_audit.py rtl_unit_test_coverage_check.py testbench_gen.py vacuous_testbench_check.py verilator_coverage_measure.py design_one_shot_runner.py::step_reference_tb design_one_shot_runner.py::step_emit_phase2_manifests | Inputs and outputsOUT phase2/stage1/sim/*.log OR phase2/stage1/sim/results.xml OR phase2/stage1/sim/pass.flag OR phase2/stage1/sim_professional/**/results.xml reports/phase2/coverage/coverage_actual.json reports/phase2/coverage/coverage_verilator.json phase2/stage1/sim/reference_tb/ref_tb.log (produced, undeclared) phase2/stage1/sim/tb/* (produced, undeclared) | done | done | missing | missing | done | done | missing | done | partial | before + afterOnly on expert reference-TB path: AI authors expected behavior, then checks evidence against L10 intent. |
| 5 🔁 Formal verification (assertions proved + bit-level full-stack phase2/stage1/tb) | abc iverilog sby yosys | 7 programsassertion_property_check.py bit_level_full_stack_tb_check.py formal_harness_gen.py formal_proof_evidence_check.py formal_property_run.py design_one_shot_runner.py::step_full_stack_tb_gen design_one_shot_runner.py::step_emit_phase2_manifests | Inputs and outputsOUT phase2/stage1/formal/*.sby OR phase2/stage1/formal/formal_authoring_request.json OR phase2/stage1/formal/formal_not_applicable.json phase2/stage1/formal/results.json OR phase2/stage1/formal/formal_authoring_request.json OR phase2/stage1/formal/formal_not_applicable.json phase2/stage1/sim_full_stack/results.json phase2/stage1/formal/property_contract.json (produced, undeclared) | done | done | missing | missing | done | done | missing | done | partial | before + afterOnly on formal fallback: AI authors proof obligations/harness, then reviews unbounded proof evidence. |
| 6 FPGA early prototype + verification report audit | quartus | 10 programsauto_diagnostic_led_synth.py debug_first_pass.py (declared, not run) fpga_led_probe_lint.py fpga_test_harness_gen.py (declared, not run) fpga_verification_audit.py quartus_map_audit.py qsf_gen.py sdc_gen.py design_one_shot_runner.py::step_fpga_compile design_one_shot_runner.py::step_emit_phase2_manifests | Inputs and outputsOUT phase2/stage1/fpga/output_files/*.sof phase2/stage1/fpga/output_files/*.map.rpt reports/phase2/fpga/quartus_map_audit.json phase2/stage1/fpga/*.qsf (produced, undeclared) phase2/stage1/fpga/*.sdc (produced, undeclared) | done | done | missing | missing | done | done | missing | done | partial | noneProgram-owned step; apply declared gates and completion auditor. |
| P0 Structural-RTL pre-flight (chip-AGNOSTIC structural gates) | iverilog ngspice opensta | 2 programsflow_step_output_content_check.py flow_compliance_check.py::_run_structural_rtl_gates (245 structural-RTL programs) | Inputs and outputsIN phase2/stage1/rtl/*.sv OR phase2/stage1/rtl/*.v OUT — | done | done | n/a | missing | done | partial | n/a | n/a | done | noneProgram-owned step; apply declared gates and completion auditor. |
| Constraints, synthesis and DFT | |||||||||||||
| 7 Constraint setup (SDC + PVT matrix) | iverilog ngspice opensta | 8 programsl21_to_upf_emit.py macro_non_seq_arc_contract_check.py pvt_matrix_check.py sdc_syntax_check.py stage1_compliance.py stage_on_pass_review.py phase3_one_shot_runner.py::step_prelayout_signoff phase3_one_shot_runner.py::step_canonicalize_artefacts | Inputs and outputsOUT phase2/stage2/constraints/*.sdc phase2/stage2/constraints/pvt_matrix.json phase3/stage3/pnr/constraint.sdc (produced, undeclared) reports/phase3/single_corner_stance.json (produced, undeclared) | done | done | missing | missing | partial | done | missing | done | partial | noneProgram-owned step; apply declared gates and completion auditor. |
| 8 🔁 SDC validation | — | 4 programsderived_clock_sdc_required_check.py sdc_exception_correlation_check.py sdc_syntax_check.py sdc_validator_check.py | Inputs and outputsIN phase2/stage2/constraints/*.sdc phase2/stage2/constraints/pvt_matrix.json phase1/generated_docs/L8_TIMING_WAVEFORM.json OUT reports/phase2/sdc_check.json | done | done | missing | missing | done | done | missing | done | partial | noneProgram-owned step; apply declared gates and completion auditor. |
| 9 Synthesis (Yosys → mapped netlist) | abc sv2v yosys | 7 programsarea_total_vs_budget_check.py pdk_consistency_check.py provenance_check.py synth_netlist_check.py synth_wrapper_gen.py (declared, not run) design_one_shot_runner.py::step_yosys_synth phase3_one_shot_runner.py::step_synth | Inputs and outputsOUT phase2/stage2/synth/netlist.v phase2/stage2/synth/area.rpt OR phase2/stage2/synth/stats.json phase2/stage2/synth/yosys.log (produced, undeclared) phase2/stage2/synth/netlist_yosys.v (produced, undeclared) provenance.jsonl (produced, undeclared) | done | done | missing | missing | done | done | missing | done | partial | noneProgram-owned step; apply declared gates and completion auditor. |
| 10 🔁 Pre-layout STA (multi-corner) | opensta | sta_report_check.py | Inputs and outputsIN phase2/stage2/synth/netlist.v phase2/stage2/constraints/*.sdc phase2/stage2/constraints/pvt_matrix.json OUT phase3/stage3/sta/pre_pnr_timing.rpt reports/phase3/sta/pre_pnr_summary.json phase3/stage3/sta/per_corner/sta_*.rpt (produced, undeclared) phase3/stage3/sta/pre_pnr_power_preview.rpt (produced, undeclared) | done | done | missing | missing | done | done | partial | done | done | noneProgram-owned step; apply declared gates and completion auditor. |
| 11 DFT insertion (scan chain + ATPG + at-speed + BSDL) | fault iverilog (via fault) yosys (via fault; also run directly for SAT stimulus when stuck-at coverage is below target) | 5 programsbsdl_emit.py dft_atpg_coverage_check.py dft_signoff_check.py fault_atpg_run.py fault_scan_chain_insert.py | Inputs and outputsIN phase2/stage2/synth/netlist.v OUT phase2/stage2/dft/scan_netlist.v phase2/stage2/dft/atpg_coverage.rpt phase2/stage2/dft/transition_atpg_plan.md reports/phase2/dft/coverage.json reports/phase2/dft/bsdl_plan.json phase2/stage2/dft/coverage.yml phase2/stage2/dft/cut_netlist.v (produced, undeclared) phase2/stage2/dft/tv.json (produced, undeclared) reports/phase2/dft/scan_chain.json (produced, undeclared) phase2/stage2/dft/*.bsdl (produced, undeclared) | done | done | missing | missing | done | done | partial | done | done | noneProgram-owned step; apply declared gates and completion auditor. |
| FS1 ISO-26262 FMEDA diagnostic-coverage (fault-injection; safety designs only) | iverilog | fmeda_coverage_check.py fmeda_fault_injection_coverage.py | Inputs and outputsIN phase2/stage1/rtl/*.sv OR phase2/stage1/rtl/*.v OUT reports/phase2/safety/fmeda_coverage.json (produced, undeclared) reports/phase2/safety/fmeda_coverage_gate.json (produced, undeclared) | done | done | missing | missing | done | done | missing | n/a | done | noneProgram-owned step; apply declared gates and completion auditor. |
| DT1 Transition-delay-fault (at-speed LOC) ATPG | fault (cut; only when step 11's cut netlist is unusable) yosys | transition_coverage_check.py transition_fault_atpg_run.py | Inputs and outputsIN — OUT reports/phase2/dft/transition_coverage.json phase2/stage2/dft/tdf/flat_core.v (produced, undeclared) | done | done | missing | missing | done | done | partial | done | done | noneProgram-owned step; apply declared gates and completion auditor. |
| 12 Post-DFT optimization (resynth / buffering) | yosys | dft_post_optimization_scan_survival_check.py | Inputs and outputsIN phase2/stage2/dft/scan_netlist.v OUT phase2/stage2/synth/post_dft_netlist.v | done | done | missing | missing | done | done | missing | done | done | noneProgram-owned step; apply declared gates and completion auditor. |
| 13 🔁 Equivalence check (RTL ≡ post-DFT netlist) | yosys | 2 programslec_equivalence_check.py lec_run.py | Inputs and outputsIN phase2/stage1/rtl/*.sv OR phase2/stage1/rtl/*.v phase2/stage2/synth/post_dft_netlist.v OUT reports/lec.rpt reports/lec.json | done | done | missing | missing | done | done | missing | done | done | noneProgram-owned step; apply declared gates and completion auditor. |
| 14 🔁 Synthesis handoff gate (pre-PnR Yosys script + netlist audit; open-source-flow specific) | — | 6 programsflow_compliance_check.py flow_step_output_content_check.py stage_on_pass_review.py yosys_hilomap_required_check.py yosys_script_template_check.py yosys_tiecell_recipe_order_check.py | Inputs and outputsIN phase2/stage2/synth/netlist.v OUT phase2/stage2/synth/netlist.v reports/analog/stage_analog_compliance.json | done | done | missing | missing | partial | partial | missing | done | done | noneProgram-owned step; apply declared gates and completion auditor. |
| DT2 Path-delay-fault (at-speed, timing-graded) ATPG | fault (cut; only when step 11's cut netlist is unusable) opensta yosys | path_delay_coverage_check.py path_delay_fault_atpg_run.py | Inputs and outputsIN reports/phase2/dft/transition_coverage.json (declared dependency) phase3/stage3/extracted/*.spef (declared dependency) OUT reports/phase2/dft/path_delay_coverage.json | done | done | missing | missing | done | done | missing | done | done | noneProgram-owned step; apply declared gates and completion auditor. |
| DT3 Small-delay-defect (SDD) at-speed grade | fault (cut; fallback only, when step 11's cut netlist is unusable) opensta (fallback only: DT2's report unreadable) yosys (fallback only: DT2's report unreadable, or DT1's report lists no faults) | sdd_atpg_run.py sdd_coverage_check.py | Inputs and outputsIN reports/phase2/dft/path_delay_coverage.json (declared dependency) reports/phase2/dft/transition_coverage.json (declared dependency) OUT reports/phase2/dft/sdd_coverage.json | done | done | missing | missing | done | done | missing | done | done | noneProgram-owned step; apply declared gates and completion auditor. |
| Step | EDA | Programs | Inputs → outputs | D1 | D2 | D3 | D4 | D5 | D6 | D7 | D8 | D9 | AI role |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Analog design and verification | |||||||||||||
| A1 Analog Spec Extraction | — | 2 programsanalog_a1_spec_emit.py analog_a1_spec_extract_check.py | Inputs and outputsIN phase1/generated_docs/L1_DATASHEET.json phase1/generated_docs/L5_ADI_SPEC.json OUT phase3/analog/*/spec.json OR phase1/analog/*/spec.json | done | done | missing | missing | done | done | missing | done | done | before + afterOnly when the spec producer cannot bind a spec (spec_gap.json): AI extracts the analog spec from L1/L5, then signs a judgement over spec.json. |
| A2 Analog Topology Selection | — | 2 programsanalog_a2_topology_emit.py analog_a2_topology_select_check.py | Inputs and outputsIN phase3/analog/*/spec.json OR phase1/analog/*/spec.json OUT phase3/analog/*/topology.md OR phase2/analog/*/topology.md phase3/analog/*/topology.json (produced, undeclared) | done | done | missing | missing | done | done | partial | done | done | before + afterOnly when the topology producer declines the block (topology_gap.json): AI selects the topology, then signs a judgement over the topology files. |
| A3 Analog Netlist Generation | ngspice | 3 programsanalog_a3_netlist_emit.py analog_a3_netlist_gen_check.py analog_netlist_pdk_check.py | Inputs and outputsIN phase3/analog/*/topology.md OR phase2/analog/*/topology.md unknown (external input path undeclared: the PDK device models / tech decks (PDK_ROOT — outside the project tree)) OUT phase3/analog/*/*.sp OR phase2/analog/*/*.sp phase3/analog/*/netlist_provenance.json (produced, undeclared) | done | done | missing | missing | done | done | partial | done | done | noneProgram-owned when the netlist producer succeeds; if it declines (netlist_gap.json), AI writes the netlist through a skill and no signed judgement follows. |
| A4 Analog Corner Sweep (PVT) | ngspice | 7 programsanalog_a4_corner_sweep_check.py analog_adc_enob_corner_check.py analog_corner_lib_realism_lint.py analog_loop_liveness_check.py analog_loop_liveness_samples_emit.py analog_real_corner_sweep.py analog_sigma_delta_gain_floor_check.py | Inputs and outputsIN phase3/analog/*/*.sp OR phase2/analog/*/*.sp phase3/analog/*/spec.json OR phase1/analog/*/spec.json OUT phase3/analog/*/corner_results.json OR phase2/analog/*/corner_results.json phase3/analog/*/sizing_loop/*.sp (produced, undeclared) phase3/analog/*/sizing_loop/*.ngspice.log (produced, undeclared) phase3/analog/*/sizing_loop/*.wrdata (produced, undeclared) phase3/analog/*/sizing_loop/results.json (produced, undeclared) phase3/analog/*/corner_sweep_native_gap.json (produced, undeclared) phase3/analog/*/loop_liveness_samples.json (produced, undeclared) phase3/analog/*/loop_liveness.json (produced, undeclared) | done | done | missing | missing | done | done | missing | done | partial | noneProgram-owned step; apply declared gates and completion auditor. |
| A5 Analog Layout | magic | 2 programsanalog_a5_layout_check.py analog_a5_layout_emit.py | Inputs and outputsIN phase3/analog/*/*.sp OR phase2/analog/*/*.sp OUT phase3/analog/*/layout.mag OR phase3/analog/*/*.gds phase3/analog/*/layout_provenance.json (produced, undeclared) phase3/analog/*/*.mag (produced, undeclared) | done | done | missing | missing | done | done | missing | done | partial | noneProgram-owned step; apply declared gates and completion auditor. |
| A6 Analog Physical Verification (per-block DRC + LVS before merge) | klayout magic | 4 programsanalog_a6_block_pv_check.py analog_a6_drc_attribute.py analog_a6_native_pv.py klayout_pdk_lvs.py | Inputs and outputsIN phase3/analog/*/layout.mag OR phase3/analog/*/*.gds OUT phase3/analog/*/drc_clean.flag OR phase3/analog/*/drc.report OR phase3/analog/*/*.lyrdb OR phase3/analog/*/drc.rpt phase3/analog/*/lvs_match.flag OR phase3/analog/*/lvs.report OR phase3/analog/*/comp.json OR phase3/analog/*/lvs.rpt phase3/analog/*/drc.rawreport (produced, undeclared) phase3/extracted/analog/*/* (produced, undeclared) | done | done | missing | missing | done | done | missing | done | partial | noneProgram-owned step; apply declared gates and completion auditor. |
| A7 🔁 Post-Layout Resimulation | — | 2 programsanalog_a7_post_layout_resim_check.py analog_pre_vs_post_layout_check.py | Inputs and outputsIN phase3/analog/*/layout.mag OR phase3/analog/*/*.gds OUT phase3/analog/*/pre_vs_post.json | done | done | missing | missing | done | done | missing | done | partial | noneNo signed AI judgement, but on a non-stub run an AI skill writes pre_vs_post.json; the declared gates and completion auditor own the verdict. |
| A8 Hardmacro Generation (LEF + Liberty + GDS + Verilog) | magic | 8 programsanalog_a8_hardmacro_gen_check.py analog_hardmacro_check.py analog_hardmacro_gds_emit.py analog_hardmacro_pinname_consistency_check.py analog_lef_gds_outline_check.py analog_macro_rtl_interface_check.py analog_topology_behaviour_check.py l21_macro_supply_rail_synth.py | Inputs and outputsIN — OUT phase3/analog/hardmacro/*/*.lef phase3/analog/hardmacro/*/*.lib phase3/analog/hardmacro/*/*.gds phase3/analog/hardmacro/*/*.v phase1/generated_docs/L21_POWER_INTENT.json (produced, undeclared) | done | done | missing | missing | partial | done | missing | done | partial | noneNo signed AI judgement, but on a non-stub run an AI skill writes the macro .lef/.lib/.v views; the declared gates and completion auditor own the verdict. |
| A9 🔁 Co-Simulation (+ HW correlation when bench data exists) | — | 8 programsanalog_a9_hw_verify_check.py, analog_hil_convergence_log_check.py, analog_hil_iteration_cap_check.py, analog_hil_report_schema_check.py, analog_hil_single_knob_check.py, analog_hw_spice_correlation_check.py, analog_hw_tb_de10lite_budget_check.py, mixed_signal_cosim_check.py | Inputs and outputsIN — OUT phase3/mixed_signal/cosim/*_cosim_results.json OR phase3/mixed_signal/cosim/mixed_signal_results.json OR phase3/analog/*/hw_measurements.json | done | done | missing | missing | done | done | missing | done | partial | before + afterWhenever A9 runs: AI selects the co-simulation scenarios, then signs a judgement bound to the SHA-256 of the cosim results, block specs and L5; until it signs, an A9 PASS is held at NOT_MEASURED, and the hardware verdict stays program-owned. |
| Step | EDA | Programs | Inputs → outputs | D1 | D2 | D3 | D4 | D5 | D6 | D7 | D8 | D9 | AI role |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Physical implementation and sign-off | |||||||||||||
| 15 Floorplan + PDN | openroad | 6 programsfloorplan_pdn_check.py ip_integration_check.py macro_obs_load_parity_check.py phase3_backend_step.py (declared, not run) stage2_compliance.py stage_on_pass_review.py | Inputs and outputsIN phase2/stage2/synth/post_dft_netlist.v phase2/stage2/constraints/*.sdc OUT phase3/stage3/pnr/floorplan.def phase3/stage3/pnr/pdn.tcl OR phase3/stage3/pnr/pdn.done reports/phase2/gates/stage2_compliance.json phase3/stage3/pnr/constraint.sdc (produced, undeclared) phase3/stage3/pnr/pnr.tcl (produced, undeclared) | done | done | missing | missing | partial | done | missing | done | partial | noneProgram-owned step; apply declared gates and completion auditor. |
| 15.5ic Pad Ring (chip/IC path only) | openroad | 5 programsio_pad_chip_top_gen.py pad_assignment_gen.py pad_bterm_coincidence_check.py pad_ring_check.py pad_ring_gen.py | Inputs and outputsIN phase3/stage3/pnr/floorplan.def input/submission_template/tapeout_declaration.json OUT phase3/stage3/pnr/padring.def reports/phase3/padring.json reports/phase3/pad_assignment.json phase3/stage3/pnr/chip_top_io.v (produced, undeclared) phase3/stage3/pnr/pad_assignment.json (produced, undeclared) phase3/stage3/pnr/padring.SKIPPED.txt (produced, undeclared) reports/phase3/io_pad_chip_top.json (produced, undeclared) reports/phase3/pad_bterm_coincidence.json (produced, undeclared) reports/phase3/supply_entry_plan.json (produced, undeclared) | done | done | missing | missing | done | done | missing | done | partial | noneProgram-owned step; apply declared gates and completion auditor. |
| 16 Clock planning | — | clock_plan_check.py | Inputs and outputsIN phase3/stage3/pnr/floorplan.def phase2/stage2/constraints/*.sdc OUT phase3/stage3/cts/clock_plan.json | done | done | missing | missing | done | done | missing | done | partial | noneProgram-owned step; apply declared gates and completion auditor. |
| 17 Placement (global + detailed) | openroad | placement_legality_check.py pnr_timing_repair_completeness_check.py | Inputs and outputsIN phase3/stage3/pnr/floorplan.def phase3/stage3/pnr/pdn.tcl OR phase3/stage3/pnr/pdn.done OUT phase3/stage3/pnr/placed.def reports/phase3/placement_legality.json | done | done | missing | missing | done | done | missing | done | partial | noneProgram-owned step; apply declared gates and completion auditor. |
| 18 Spare-cell + ECO-prep insertion (Design-for-ECO) | openroad | spare_cell_coverage_check.py | Inputs and outputsIN phase3/stage3/pnr/placed.def OUT phase3/stage3/pnr/spare_cells.json reports/spare_cell_coverage.json | done | done | missing | missing | done | done | missing | done | partial | noneProgram-owned step; apply declared gates and completion auditor. |
| 19 CTS (Clock Tree Synthesis) | openroad | cts_quality_check.py | Inputs and outputsIN phase3/stage3/pnr/placed.def phase3/stage3/cts/clock_plan.json OUT phase3/stage3/pnr/post_cts.def phase3/stage3/cts/clock_tree.rpt phase3/stage3/cts/clock_tree.json (produced, undeclared) | done | done | missing | missing | done | done | missing | done | partial | noneProgram-owned step; apply declared gates and completion auditor. |
| 20 🔁 Post-CTS hold fixing | openroad opensta | 2 programshold_area_budget_check.py (declared, not run) hold_closure_check.py | Inputs and outputsIN phase3/stage3/pnr/post_cts.def OUT phase3/stage3/pnr/post_hold.def phase3/stage3/pnr/post_hold_timing.rpt (produced, undeclared) | done | done | missing | missing | done | done | missing | done | done | noneProgram-owned step; apply declared gates and completion auditor. |
| 21 Routing (global + detailed) | openroad opensta | 5 programsdef_stage_progression_check.py drc_report_check.py macro_obs_geometry_intersect_check.py provenance_check.py route_congestion_trade_disclosure.py | Inputs and outputsIN phase3/stage3/pnr/post_hold.def OUT phase3/stage3/pnr/routed.def phase3/stage3/pnr/openroad.log phase3/stage3/pnr/routed.drc.rpt reports/phase3/drc_router.rpt reports/phase3/drc_router.json phase3/stage3/pnr/*_pnr.v (produced, undeclared) phase3/stage3/pnr/sta.rpt (produced, undeclared) | done | done | missing | missing | done | done | missing | done | done | noneProgram-owned step; apply declared gates and completion auditor. |
| 22 Parasitic Extraction (RC → SPEF) | openroad | provenance_check.py spef_extraction_check.py | Inputs and outputsIN phase3/stage3/pnr/routed.def OUT phase3/stage3/extracted/parasitic.spef OR phase3/stage3/extracted/*.spef reports/phase2/gates/spef_extraction.json | done | done | missing | missing | done | done | missing | done | done | noneProgram-owned step; apply declared gates and completion auditor. |
| 23 🔁 Post-route STA (multi-corner multi-mode sign-off) | openroad opensta | 10 programsachieved_period_recorded_check.py clock_target_record_agreement_check.py drv_promotion_corroboration_check.py hold_corner_coverage_check.py post_route_signoff_corner_check.py sta_achievable_fmax_report.py sta_architectural_residual_check.py sta_assumed_clock_disclosure_check.py sta_corner_record_completeness_check.py sta_report_check.py | Inputs and outputsIN phase3/stage3/extracted/parasitic.spef OR phase3/stage3/extracted/*.spef phase2/stage2/constraints/*.sdc phase2/stage2/constraints/pvt_matrix.json OUT phase3/stage3/sta/post_route_timing.rpt reports/phase3/sta_spef_based.rpt reports/phase3/sta/post_route_summary.json reports/phase3/sta/sta_corner_record_completeness.json reports/phase3/sta/post_route_signoff_corner.json reports/phase3/sta/architectural_residual.json phase3/stage3/sta/sta_spef_based.rpt (produced, undeclared) phase3/stage3/sta/sta_spef_multicorner.rpt (produced, undeclared) phase3/stage3/sta/sta_mcorner_ocv.rpt (produced, undeclared) reports/phase3/sta_mcorner_ocv.rpt (produced, undeclared) phase3/stage3/extracted/spef_corners/*.spef (produced, undeclared) reports/phase3/multi_corner_spef_stance.json (produced, undeclared) reports/phase3/mcorner_ocv_stance.json (produced, undeclared) reports/phase3/achievable_fmax.json (produced, undeclared) | done | done | missing | missing | done | done | missing | done | done | noneProgram-owned step; apply declared gates and completion auditor. |
| 24 🔁 IR Drop (static + dynamic) | openroad | 3 programsdynamic_ir_drop_check.py dynamic_ir_vectored_emit.py ir_drop_report_check.py | Inputs and outputsIN phase3/stage3/pnr/routed.def phase3/stage3/pnr/pdn.tcl OR phase3/stage3/pnr/pdn.done OUT reports/phase3/ir_drop.rpt reports/phase3/ir_drop.json reports/phase3/ir_drop_signoff.json reports/phase3/dynamic_ir.json | done | done | missing | missing | done | done | missing | done | done | noneProgram-owned step; apply declared gates and completion auditor. |
| 25 🔁 EM check (electromigration lifetime) | openroad | em_peak_current_authority_check.py em_report_check.py | Inputs and outputsIN phase3/stage3/pnr/routed.def reports/phase3/ir_drop.rpt reports/phase3/ir_drop.json reports/phase3/ir_drop_signoff.json reports/phase3/dynamic_ir.json OUT reports/phase3/em.rpt reports/phase3/em.json reports/phase3/em_signoff.json reports/phase3/em_current_authority.json reports/phase3/em_segments.csv (produced, undeclared) reports/phase3/em_pg_geometry.tsv (produced, undeclared) reports/phase3/em_pg_geometry_subject.json (produced, undeclared) | done | done | missing | missing | done | done | missing | done | done | noneProgram-owned step; apply declared gates and completion auditor. |
| 26 🔁 Antenna check (gate-oxide protection) | klayout openroad | antenna_report_check.py gds_antenna_deck_check.py | Inputs and outputsIN phase3/stage3/pnr/routed.def OUT reports/phase3/antenna.rpt reports/phase3/antenna.json reports/phase3/antenna_signoff.json | done | done | missing | missing | partial | done | missing | done | done | noneProgram-owned step; apply declared gates and completion auditor. |
| 26.5ic Die Finishing — seal ring + die identification (chip/IC path only) | klayout | die_finishing_check.py die_finishing_gen.py | Inputs and outputsIN phase3/stage3/pnr/routed.def input/submission_template/tapeout_declaration.json OUT phase3/stage3/pnr/die_finished.def OR phase3/stage3/pnr/die_finishing.SKIPPED.txt reports/phase3/die_finishing.json phase3/stage3/pnr/*.gds (produced, undeclared) | done | done | missing | missing | partial | done | missing | done | done | noneProgram-owned step; apply declared gates and completion auditor. |
| 27 🔁 Signal Integrity (Crosstalk / Noise / Glitch + MCF crosstalk-delay) | openroad opensta | 7 programsflow_step_output_content_check.py si_crosstalk_check.py si_mcf_repair.py si_mcf_sta.py si_mcf_sta_check.py si_mcf_verdict_basis.py si_signoff_timing_aware.py | Inputs and outputsIN phase3/stage3/extracted/parasitic.spef OR phase3/stage3/extracted/*.spef OUT reports/phase3/si_crosstalk.rpt OR reports/phase3/si_crosstalk.json reports/phase3/si_mcf_sta.json reports/phase3/si_mcf_sta.rpt reports/phase3/si_mcf_repair.json (produced, undeclared) reports/phase3/si_crosstalk_timing_aware.rpt (produced, undeclared) phase3/stage3/extracted/*_si_timing_aware.json (produced, undeclared) phase3/stage3/extracted/si_mcf/*.spef (produced, undeclared) phase3/stage3/extracted/si_mcf/si_mcf_windows.json (produced, undeclared) | done | done | missing | missing | done | done | missing | done | done | noneProgram-owned step; apply declared gates and completion auditor. |
| 28 🔁 PERC / Reliability sign-off (ESD + latch-up + cross-domain) | — | 2 programslatchup_esd_spacing_check.py perc_signoff_check.py | Inputs and outputsIN phase3/stage3/pnr/routed.def OUT reports/phase3/perc_equivalent.json reports/phase3/perc_equivalent.rpt reports/phase3/PERC_SIGNOFF_MEMO.md reports/phase2/gates/perc_signoff.json | done | done | missing | missing | partial | done | missing | done | done | noneProgram-owned step; apply declared gates and completion auditor. |
| 29 Post-Layout Gate-Level Simulation (Post-Sim + SDF) | iverilog openroad | 3 programspost_layout_sim_check.py sdf_gate_sim.py synth_wrapper_check.py | Inputs and outputsIN phase2/stage2/synth/post_dft_netlist.v OUT phase3/stage3/sim_postlayout/results.log OR phase3/stage3/sim_postlayout/pass.flag reports/phase2/gates/post_layout_sim.json phase3/stage3/sim_postlayout/*.sdf (produced, undeclared) phase3/stage3/sim_postlayout/sdf_sim_skipped.json (produced, undeclared) | done | done | missing | missing | partial | done | missing | done | done | noneProgram-owned step; apply declared gates and completion auditor. |
| 30 Post-Layout SPICE Verification (critical-path correlation + analog) | ngspice opensta | spice_correlation_check.py | Inputs and outputsIN unknown (external input path undeclared: the PDK device models / tech decks (PDK_ROOT — outside the project tree)) OUT phase3/stage3/spice/*.sp OR phase3/stage3/spice/*.spice OR sim_spice/*.sp phase3/stage3/spice/correlation.json OR reports/phase3/spice_correlation.json phase3/stage3/spice/spice_correlation_not_run.json (produced, undeclared) | done | done | missing | missing | done | done | missing | done | done | noneProgram-owned step; apply declared gates and completion auditor. |
| 32 🔁 Post-route timing repair pass (multi-corner repair_design + repair_timing + reroute) | openroad opensta | 3 programsflow_step_output_content_check.py postroute_timing_repair_audit.py postroute_timing_repair_status_gen.py | Inputs and outputsIN — OUT phase3/stage3/postroute_timing_repair/repair_log.json OR phase3/stage3/postroute_timing_repair/no_repair_needed.flag phase3/stage3/postroute_timing_repair/postroute_timing_repair_decision.json phase3/stage3/postroute_timing_repair/postroute_timing_repair.tcl (produced, undeclared) phase3/stage3/postroute_timing_repair/timing_repaired.def (produced, undeclared) phase3/stage3/postroute_timing_repair/*_timing_repaired.v (produced, undeclared) phase3/stage3/sta/sta_mcorner_ocv_postrepair.rpt (produced, undeclared) | done | done | missing | missing | partial | done | partial | done | done | noneProgram-owned step; apply declared gates and completion auditor. |
| Output and handoff | |||||||||||||
| 33 Power analysis (pre/post-layout) | opensta | 3 programspower_report_check.py power_total_vs_budget_check.py upf_syntax_check.py | Inputs and outputsIN phase3/stage3/extracted/parasitic.spef OR phase3/stage3/extracted/*.spef OUT reports/phase3/power.rpt reports/phase3/power.json | done | done | missing | missing | done | done | missing | done | partial | noneProgram-owned step; apply declared gates and completion auditor. |
| 34 Metal Fill (ECO-aware density fill insertion) | klayout openroad | 3 programsmetal_fill_density_check.py metal_fill_emit.py spare_cell_preservation_check.py | Inputs and outputsIN phase3/stage3/pnr/routed.def phase3/stage3/pnr/spare_cells.json OUT phase3/stage3/pnr/filled.def OR phase3/stage3/pnr/metal_fill.done reports/density.json OR reports/phase3/density.json reports/density.rpt OR reports/phase3/density.rpt | done | done | missing | missing | done | done | missing | done | done | noneProgram-owned step; apply declared gates and completion auditor. |
| 35 DFM screen (CMP density + redundant-via ratio + foundry-side OPC/RET disclosure) | — | 2 programsdfm_screen_check.py flow_step_output_content_check.py | Inputs and outputsIN phase3/stage3/pnr/filled.def OR phase3/stage3/pnr/metal_fill.done reports/density.json OR reports/phase3/density.json reports/density.rpt OR reports/phase3/density.rpt OUT reports/phase3/dfm_screen.json | done | done | missing | missing | done | n/a | missing | done | done | noneProgram-owned step; apply declared gates and completion auditor. |
| 36 Tapeout checklist (final sign-off confirmation) | — | 6 programsdeclared_pdk_is_the_pdk_used_check.py ppa_head_to_head_check.py report_belongs_to_project_check.py step_internal_fail_bubble_up_check.py tapeout_checklist_gen.py tapeout_signoff_check.py | Inputs and outputsIN — OUT reports/audit/tapeout_checklist.json | done | done | missing | missing | partial | done | missing | done | partial | afterOnly when waivers or unresolved items exist: AI reviews their design meaning before sign-off. |
| 37 GDSII output (after routed-layout pre-stream admission) | klayout magic | 16 programsdef_gds_port_power_restore.py die_density_fill_gen.py die_finishing_gen.py drc_feedback_repair.py flow_stage_check.py gate_evidence_completeness_check.py gds_ip_attribution.py gds_port_label_check.py gds_size_check.py gds_substance_check.py layout_receipt_identity_check.py metal_fill_emit.py provenance_check.py reported_figure_artifact_backing_check.py stage3_compliance.py stage_on_pass_review.py | Inputs and outputsIN phase3/stage3/pnr/filled.def OR phase3/stage3/pnr/metal_fill.done OUT phase3/stage4/gds/*.gds phase3/stage3/pnr/*stream_out.log reports/phase3/pad_ring_route_evidence.json reports/phase3/gates/stage3_compliance.json reports/phase3/layout_receipts.json phase3/stage3/pnr/*.prefinish.gds (produced, undeclared) phase3/stage3/pnr/*.prefinish.gds.receipt.json (produced, undeclared) phase3/stage3/pnr/stream_out.py (produced, undeclared) reports/phase3/die_density_fill.json (produced, undeclared) reports/phase3/cmp_fill_emit.json (produced, undeclared) reports/phase3/drc_feedback.json (produced, undeclared) | done | done | missing | missing | done | n/a | partial | done | partial | noneProgram-owned step; apply declared gates and completion auditor. |
| 37.3 GDS stream-out / finishing fidelity — the shipped GDS XOR'd against this run's own pre-finishing boundary | klayout | gds_xor_check.py | Inputs and outputsIN — OUT reports/phase3/gds_xor.json | done | done | missing | missing | partial | done | missing | done | done | noneProgram-owned step; apply declared gates and completion auditor. |
| 31 🔁 Physical Verification (DRC + LVS + ERC + Density) | klayout magic netgen openroad | 17 programsdrc_report_check.py drc_vacuous_pass_check.py erc_density_check.py gate_verilog_to_spice.py klayout_pdk_lvs.py lvs_report_check.py lvs_signoff_guard.py lvs_triage_classify.py (declared, not run) magic_illegal_overlap_check.py magic_illegal_overlap_record_check.py mcp_execution_verify.py perc_corpus_sweep.py pg_rail_geometry_check.py pnr_via_stack_completeness_check.py (declared, not run) provenance_check.py sweep_reach_check.py waiver_growth_check.py | Inputs and outputsIN phase3/stage3/pnr/routed.def OUT reports/phase3/drc_signoff.rpt reports/phase3/lvs.rpt reports/phase3/erc.rpt reports/phase3/lvs.json reports/phase2/gates/erc_density.json reports/phase3/magic_illegal_overlap.json reports/phase3/lvs_verdict.json reports/phase3/drc_signoff.json reports/phase3/perc_sweep.json reports/phase3/drc_signoff_magic.rpt (produced, undeclared) reports/phase3/drc_signoff_magic.json (produced, undeclared) reports/phase3/erc.json (produced, undeclared) | done | done | missing | missing | done | done | partial | done | partial | noneProgram-owned step; apply declared gates and completion auditor. |
| 37.4 Sign-off metrics aggregation — the run's own checker verdicts, under the names the release documents read | — | signoff_metrics_aggregate.py | Inputs and outputsIN phase3/stage4/gds/*.gds OUT phase3/final/metrics.json reports/phase3/signoff_metrics_aggregate.json | done | done | missing | missing | partial | n/a | missing | done | done | noneProgram-owned step; apply declared gates and completion auditor. |
| 37.5ip Digital Hardmacro Generation — LEF + Liberty + GDS + Verilog (delivered on EVERY route) | magic opensta | 4 programsdigital_hardmacro_check.py digital_hardmacro_gen.py ip_release_docs_gen.py release_docs_check.py | Inputs and outputsIN phase3/stage4/gds/*.gds OUT phase3/stage4/hardmacro/*.lef phase3/stage4/hardmacro/*.lib phase3/stage4/hardmacro/*.gds phase3/stage4/hardmacro/*.v reports/phase3/digital_hardmacro.json phase3/stage4/documentation/ip/*/IP_DATASHEET.md phase3/stage4/documentation/ip/*/IP_INTEGRATION_GUIDE.md phase3/stage4/documentation/ip/*/RELEASE_NOTES.md phase3/stage4/documentation/ip/*/ERRATA.md phase3/stage4/documentation/ip/*/DELIVERABLES_MANIFEST.md phase3/stage4/documentation/ip/*/documentation_manifest.yaml | done | done | missing | missing | done | done | missing | done | done | noneProgram-owned step; apply declared gates and completion auditor. |
| 37.5ic Tape-out Precheck — our general ladder, plus the operator's own refusal where the PDK ships one (chip/IC path only) | — | 7 programsclosed_loop_executed_reentry_census.py closed_loop_metric_reaches_its_producer.py every_required_metric_key_has_a_producer.py ic_release_docs_gen.py release_docs_check.py tapeout_docs_gen.py tapeout_precheck.py | Inputs and outputsIN phase3/stage4/gds/*.gds input/submission_template/tapeout_declaration.json OUT reports/phase3/tapeout_precheck.json reports/phase3/general_precheck.json reports/phase3/shuttle_precheck.json reports/phase3/docs/SIGNOFF_*.html reports/phase3/docs/BRIEF_*.html phase3/stage4/documentation/ic/*/PRELIMINARY_DATASHEET.md phase3/stage4/documentation/ic/*/RELEASE_NOTES.md phase3/stage4/documentation/ic/*/ERRATA.md phase3/stage4/documentation/ic/*/documentation_manifest.yaml | done | done | missing | missing | partial | done | missing | done | partial | noneProgram-owned step; apply declared gates and completion auditor. |
| 38 Foundry Handoff (mask spec + WAT plan + scribe layout + corner test kit) | — | foundry_handoff_pack_gen.py foundry_handoff_package_check.py | Inputs and outputsIN phase3/stage4/gds/*.gds OUT phase3/stage4/foundry_handoff/mask_spec.json phase3/stage4/foundry_handoff/wat_plan.json phase3/stage4/foundry_handoff/scribe_line_layout.gds OR phase3/stage4/foundry_handoff/scribe_line_layout.PENDING_FOUNDRY.txt phase3/stage4/foundry_handoff/corner_test_vectors.json phase3/stage4/foundry_handoff/*.gds (produced, undeclared) phase3/stage4/foundry_handoff/README.txt (produced, undeclared) reports/phase3/foundry_handoff_audit.json (produced, undeclared) | done | done | missing | missing | done | done | partial | done | done | noneProgram-owned step; apply declared gates and completion auditor. |
| 39 FPGA final sign-off (recompile + on-board test) | — | 7 programsbringup_plan_gen.py (declared, not run) fpga_on_board_attestation_check.py hw_vs_rtl_verdict_check.py signaltap_recompile_sequence_check.py (declared, not run) signaltap_stp_completeness_check.py (declared, not run) stage4_compliance.py stage_on_pass_review.py | Inputs and outputsIN phase2/stage1/rtl/*.sv OR phase2/stage1/rtl/*.v unknown (external input path undeclared: a physical FPGA board on the bench) OUT phase2/stage1/fpga/final/*.sof reports/phase2/fpga/on_board_pass.json reports/phase2/fpga/quartus_pgm.log (produced, undeclared) reports/phase2/fpga/on_board_evidence/*.log (produced, undeclared) | done | done | missing | missing | done | done | partial | done | done | noneProgram-owned step; apply declared gates and completion auditor. |
| Manufacturing and test | |||||||||||||
| 40 Fabrication (foundry mask-set + wafer fab — external) | — | manufacturing_fab_intake_check.py | Inputs and outputsIN phase3/stage4/foundry_handoff/mask_spec.json phase3/stage4/foundry_handoff/wat_plan.json phase3/stage4/foundry_handoff/scribe_line_layout.gds OR phase3/stage4/foundry_handoff/scribe_line_layout.PENDING_FOUNDRY.txt phase3/stage4/foundry_handoff/corner_test_vectors.json OUT phase3/stage5_manufacturing/mask_set_received.json phase3/stage5_manufacturing/wafer_lot_received.json | done | done | missing | missing | done | done | missing | done | done | noneProgram-owned step; apply declared gates and completion auditor. |
| 41 Wafer Sort / Probe Test (ATE + probe card) | — | wafer_sort_yield_check.py | Inputs and outputsIN phase3/stage5_manufacturing/wafer_lot_received.json OUT phase3/stage5_manufacturing/wafer_sort_yield.json phase3/stage5_manufacturing/wafer_map.csv | done | done | missing | missing | done | done | missing | done | done | noneProgram-owned step; apply declared gates and completion auditor. |
| 42 Packaging (assembly: wirebond / FC-CSP / WLCSP) | — | packaging_intake_check.py | Inputs and outputsIN phase3/stage5_manufacturing/wafer_sort_yield.json phase3/stage5_manufacturing/wafer_map.csv OUT phase3/stage5_manufacturing/packaging_log.json | done | done | missing | missing | done | done | missing | done | done | noneProgram-owned step; apply declared gates and completion auditor. |
| 43 Final Test (ATE: functional + parametric + burn-in) | — | final_test_attestation_check.py | Inputs and outputsIN phase3/stage5_manufacturing/packaging_log.json OUT phase3/stage5_manufacturing/final_test_yield.json phase3/stage5_manufacturing/burn_in_results.json | done | done | missing | missing | done | done | missing | done | done | noneProgram-owned step; apply declared gates and completion auditor. |
| 44 Reliability qualification (HTOL / FIT attestation) | — | htol_attestation_check.py | Inputs and outputsIN phase3/stage5_manufacturing/final_test_yield.json phase3/stage5_manufacturing/burn_in_results.json OUT phase3/stage5_manufacturing/htol_results.json | done | done | missing | missing | done | done | missing | done | done | noneProgram-owned step; apply declared gates and completion auditor. |
| Step | EDA | Programs | Inputs → outputs | D1 | D2 | D3 | D4 | D5 | D6 | D7 | D8 | D9 | AI role |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Mixed-signal integration | |||||||||||||
| M1 Mixed-Signal Top-Level Integration (A+D GDS merge + macro placement) | klayout magic netgen | mixed_signal_merge_check.py mixed_signal_top_lvs_run.py | Inputs and outputsIN phase3/stage4/gds/*.gds phase3/analog/hardmacro/*/*.lef phase3/analog/hardmacro/*/*.lib phase3/analog/hardmacro/*/*.gds phase3/analog/hardmacro/*/*.v OUT phase3/mixed_signal/top_merged.gds reports/analog/mixed_signal/merge.json reports/analog/mixed_signal/top_lvs.json (produced, undeclared) reports/analog/mixed_signal/top_lvs.rpt (produced, undeclared) phase3/mixed_signal/*_merged_extracted.sp (produced, undeclared) phase3/mixed_signal/macro_placements.json (produced, undeclared) phase3/mixed_signal/merge.json (produced, undeclared) | done | done | missing | missing | done | done | partial | done | done | noneProgram-owned step; apply declared gates and completion auditor. |
| M2 Mixed-Signal Power Domain + Level Shifter / Isolation Verification | — | 4 programsisolation_cell_required_check.py level_shifter_required_check.py power_domain_crossing_check.py power_domain_signal_crossing_check.py | Inputs and outputsIN phase3/mixed_signal/top_merged.gds OUT reports/analog/mixed_signal/power_domain.json reports/analog/mixed_signal/level_shifter.json reports/analog/mixed_signal/isolation.json | done | done | missing | missing | done | done | missing | done | done | noneProgram-owned step; apply declared gates and completion auditor. |
| M3 Mixed-Signal Verification (AMS co-sim + RNM + interface signal integrity) | — | mixed_signal_cosim_check.py mixed_signal_interface_si_check.py | Inputs and outputsIN phase3/mixed_signal/top_merged.gds OUT phase3/mixed_signal/cosim/mixed_signal_results.json reports/analog/mixed_signal/interface_si.json | done | done | missing | missing | done | done | missing | done | done | noneProgram-owned step; apply declared gates and completion auditor. |
| M4 Mixed-Signal Sign-Off (top-level PV + final verdict) | — | mixed_signal_signoff_check.py | Inputs and outputsIN phase3/mixed_signal/top_merged.gds OUT reports/analog/mixed_signal/signoff.json | done | done | missing | missing | done | done | missing | done | done | noneProgram-owned step; apply declared gates and completion auditor. |
The role column identifies eight conditional AI-key steps: D1, 1, 4, 5, A1, A2, A9 and 36. Seven need judgement before and after the program; one needs it after. The other 62 steps are classified as program-owned. These are role assignments, not evidence that AI signed off a run.
A waiting step should remain NOT_MEASURED(awaiting_agent_pass) until a signed judgement names the reviewer, decision and hashes of reviewed inputs, and the rerun consumes that judgement. The supplied census and completion audits do not establish a per-step signed AI-pass ledger. AI execution is therefore unknown here.
Program checks should answer mechanical questions first. AI reviews the exact program evidence and resolves source intent where a deterministic check cannot decide it. A rejected design claim needs a prompt-derived executable test before repair.
Ordered by impact on getting ICs to PASS. Status reflects the 24 September 2026 review, not a live release verdict.
Adopt a post-route repair candidate only after sign-off DRC and LVS pass; validate the pending repeatability repair and re-audit the exact combined design tree.
Repair post-route placement legality and the slow-corner path in the second audited design; remeasure final sign-off.
Bind reused outputs and STA reports to this run’s exact inputs, code, tool and PDK identity; stop derived values flowing back into input.
Close first-declaration and in-place rewrite provenance gaps, then prove D9 verdict propagation on a valid run corpus. The routed-DEF attribution fix is FIXED narrowly.
Prove that eight conditional AI handoffs wait for signed judgement; close D2, D6 and D8 blind spots with blocking checks. The bounded Phase 2 rerun repair is FIXED narrowly; a Phase 3 window remains OPEN.
The two cited design completion audits both ended FAIL. Per-step audit status from those distinct older runs does not turn this source census into a current IC verdict.
Read the user manual or watch the 15-part video series and its episode outlines.
User manual · Video episode outlines · YouTube · 中文 · Vimeo · English
This section tests the claims made by the 70-step checklist table above against the plugin source at repository commit 3c5296cbc on 2026-09-25. It reviews the table, not a chip; nothing here says whether any IC passes or fails. A finding marked STALE means the cell was correct when the page was published on 2026-09-24 and the source has changed since.
Applied. These findings were applied to the table above on 2026-09-25 against commit 40cc2c66d, after a second propose-and-challenge pass re-derived every cell on that newer source. The findings below remain the record of what the table said at publication.
The kept findings by column are: EDA 38, D6 22, Programs 17, D5 9, Inputs → outputs 8, D2 7, D9 5, AI role 4, Step name or section 2, D3/D7 1, D8 1. The skeptic confirmed 81 findings as raised and downgraded 33. Thirty of the downgrades moved a finding from WRONG to MISLEADING, mostly because the page states its own basis for the EDA column. The 42 refuted findings were 20 in Inputs → outputs, 9 in Programs, 8 in AI role, 3 in EDA and 2 in D7. All 27 STALE findings trace to four commits that landed on 2026-09-25: e2975ceff (PR #2595), ac2104931 (PR #2635), and 4e36f3703 with fd809a4c9. An editor regex scan of every cell in all 70 rows found no foundry, process-node, hostname, IP-address or local-path string, and the skeptic scans of rows A4–M4, which also covered customer-design names, found none.
Six reviewer passes each took about twelve rows and challenged every column against the source. An independent skeptic pass then re-checked each finding, confirming it, downgrading its verdict, or refuting it, and re-tested a sample of cells the reviewer had called correct. Both passes were run by AI agents working from the repository, not by a human auditor. Sources were the plugin tree at 3c5296cbc and the publication state at a2144edd1, the last main commit of 2026-09-24; rows 10–A3 were checked on snapshot b236f87e9, which reproduces the published grid. The evidence is flow/phase1_phase2_phase3.yaml, program source, git history, and re-runs of the plugin’s own checkers and matrix ledger tests (programs/flow_gate_grid.py, programs/flow_step_can_fail_check.py, programs/flow_dependency_graph_check.py, programs/tests/test_matrix_d*.py). No design was run, so D3 can only confirm that output substance is NOT_MEASURED and whether a D3 cell applies at all; it cannot say whether any output is correct.
WRONG The cell is false under the page’s own definition of the column. MISLEADING The cell is defensible on the page’s stated basis, but a reader would draw a false conclusion from it, for example a tool that appears only in a comment. STALE The cell was correct on 2026-09-24 and has changed since. Paths are relative to the plugin root vibe-ic-marketplace/plugins/vibe-ic/; tools/d9_flow_gate_reality.py is at the repository root.
| Step | Field | Table says | Verdict | What is true | Evidence |
|---|---|---|---|---|---|
| 47 rowsD1, 0.5ic, 1, 2, 3, 4, 5, 6, P0, 7, 8, 9, A4, A5, A6, A7, A8, A9, 15, 15.5ic, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 26.5ic, 27, 28, 29, 30, 38, 39, 40, 41, 42, 43, 44, M1, M2, M3, M4 | D9 | missing: “NOT_DERIVABLE_FROM_SOURCE per flow_gate_grid.py; repo-root D9 tool lacks required published corpus.” | MISLEADINGThe cited tool answers a different question. The plugin decides this one from source. | D9 can be derived from source. The plugin’s ledger test runs the page’s exact chain (step FAIL → overall FAIL → nonzero exit) and passed for all 47 rows. It discloses two limits: L3 uses a files_exist stand-in gate, and the runner edge is checked by AST only. The phase-2 --strict-structural audit treats FAILs of steps 1–40 as informational. The honest cell is “done with a disclosed stand-in” or “partial”, not “not derivable”. | programs/tests/test_matrix_d9_verdict_consumed.py: 47/47 passed at 3c5296cbc, and 30 of them re-run at a2144edd1 also passed. tools/d9_flow_gate_reality.py:4, :18–21 (measures “is the output CORRECT”). programs/flow_gate_grid.py:127–133; programs/flow_compliance_check.py:20621–20625 |
| 7 rowsD1, 2, 4, 6, 8, 9, 39 | D6 | n/a: “no condition in flow YAML; skip classification not applicable.” | WRONGConditional skips exist at clause level. | The gates carry clause-level condition_files_exist with absent_condition_reason, which are the conditional skips the page’s D6 question asks about. D6 applies, and the plugin’s D6 ledger marks these cells ENFORCED. | programs/flow_gate_grid.py:212–215 (d6_skip reads only a step-level condition); programs/flow_compliance_check.py:12558–12585; programs/tests/test_matrix_d6_skip_discipline.py passed at both commits |
| 11 rows14, 15, 18, 23, 26, 27, 31, 32, 33, 34, 36 | D6 | n/a: “no condition in flow YAML; skip classification not applicable.” | MISLEADINGSame facts as the WRONG row above; other skeptics graded it MISLEADING. | Each step has at least one gate clause with condition_files_exist and absent_condition_reason; some also have vacuous-pass tiers. D6 applies and is disclosed, so the state should be done. | flow/phase1_phase2_phase3.yaml, gate clauses of each step (the same at a2144edd1); programs/tests/test_matrix_d6_skip_discipline.py (“Dimension 6 has no NA cell”, :3006–3013) |
| 18 rows0.5ic, 3, 5, P0, 10, 13, 16, 17, 19, 20, 21, 22, 24, 25, 28, 29, 30, 38 | D6 | n/a: “no condition in flow YAML; skip classification not applicable.” | MISLEADINGLiterally true of the YAML key, but vacuous-pass or skip tiers exist. | These steps have no conditional clause, but they do have disclosed vacuous-pass or skip paths: a gate rc=2 folds to VACUOUS_PASS, or the program writes SKIPPED/NOT_MEASURED tiers. The page defines D6 to include vacuous passes, so D6 applies. The D6 ledger, run for 16 of these 18 steps, marks them ENFORCED. | programs/flow_compliance_check.py:4536–4541 and _check_program_exit_zero (rc=2 → VACUOUS_PASS); e.g. programs/lec_equivalence_check.py:626–657, programs/foundry_handoff_package_check.py:1146 |
| 20 rowsFS1, DT1, A1, A2, A3, A4, A5, A6, A7, A8, A9, 40, 41, 42, 43, 44, M1, M2, M3, M4 | D6 | partial: “condition_kind undeclared (recorded baseline).” | STALEChanged by e2975ceff (PR #2595, merged 2026-09-25 00:07 +0800). | All 20 steps now declare condition_kind (setup_required for FS1, design_dependent for the rest). D6_BASELINE is empty and the grid lists no condition without a kind, so these cells now read done. | programs/flow_gate_grid.py:109 (D6_BASELINE = set()); flow/phase1_phase2_phase3.yaml condition_kind on each step |
| 7 rows1, P0, 14, 18, 27, 32, 35 | D2 | partial: “files_exist only” (1, 18, 27, 32, 35), “no gate key at all” (P0), “only advisory/optional program_exit_zero” (14). | STALEChanged by e2975ceff (PR #2595). | Six of the seven gained a blocking flow_step_output_content_check clause; at 18, spare_cell_coverage_check became blocking. All 70 steps can now fail on content. For P0, the structural umbrella could already fail on RTL content when the page was published, so “partial” understated it even then. | programs/flow_step_can_fail_check.py: “63 can fail, 7 cannot” at a2144edd1 → “70 can fail, 0 cannot” at 3c5296cbc |
| Step | Field | Table says | Verdict | What is true | Evidence |
|---|---|---|---|---|---|
| Document extraction | |||||
| D1Phase 1 Doc Extraction (17 skills + dialogue entry → L1-L27) | EDA | magic | MISLEADINGProse mention only. | No D1 program invokes Magic. The name appears in a docstring and in an error message. | programs/l21_macro_supply_rail_declared_check.py:54, :986 |
| D1 | Inputs → outputs | OUT lists required_outputs only. | MISLEADINGA declared program output is omitted. | The declared outputs also include phase1/generated_docs/L22_VERIFICATION_PLAN.json (from l22_analog_verification_plan_emit). | flow/phase1_phase2_phase3.yaml, step D1 program_outputs |
| RTL generation and verification | |||||
| 1Spec-to-RTL | EDA | iverilog, yosys | MISLEADINGComment-only mention. | None of the listed step-1 programs invokes iverilog or yosys. | programs/ip_catalog_pull.py:330 (comment) |
| 1 | Programs | 3 programs | STALEChanged by e2975ceff. | Now 4 programs: flow_step_output_content_check.py was added to the gate. | flow/phase1_phase2_phase3.yaml, step 1 gate |
| 1 | Programs | arith_declaration_emit, ip_catalog_pull, staged_rtl_reused_ip_manifest_emit | MISLEADINGLists side emitters for a Spec-to-RTL row. | The RTL is written by the class generators (aid_class_rtl_gen.py, data_converter_rtl_gen.py) or, for 10 classes, by AI through spec-to-rtl. ip_catalog_pull runs only through the catalog-glue-author skill. | programs/design_one_shot_runner.py:7627; programs/ic_class_registry.json; skills/catalog-glue-author/SKILL.md:41, :76 |
| 1 | Inputs → outputs | OUT phase2/stage1/rtl/*.sv OR *.v | MISLEADINGDeclared program outputs are omitted. | The declared outputs also include phase2/stage1/rtl/SOURCE_MANIFEST.json and plugin_output/declaration.json. | flow/phase1_phase2_phase3.yaml, step 1 program_outputs |
| 2RTL validation (rewrite fidelity + lint + Quartus-unsafe patterns + RTL-bug claim schema) | EDA | “11 programs” abc, iverilog, klayout, magic, netgen, ngspice, openroad, opensta, sby, verilator, yosys | MISLEADING10 of the 11 names are auditor prose, and the list is mislabelled as programs. | The step-2 programs invoke only yosys. The other 10 names are comments and strings in flow_compliance_check.py. The label should read “11 tools”. | programs/crosslayer_rewrite_equivalence.py:740; programs/flow_compliance_check.py:2948, :14445 |
| 2 | Programs | 22 programs | MISLEADINGOne listed program is not run by step 2. | crosslayer_rewrite_equivalence produces the report that step 2 judges, but step 2 does not run it. crosslayer_search_space is used in-flow as a library. | programs/crosslayer_rewrite_equivalence_check.py:243–245; programs/design_one_shot_runner.py:12157 |
| 2 | Inputs → outputs | OUT lists required_outputs only. | MISLEADINGIN is correct. OUT omits a declared program output. | The declared outputs also include reports/phase2/gates/slot_pad_budget.json. | flow/phase1_phase2_phase3.yaml, step 2 program_outputs |
| 4Simulation (testbench-based + L10/L12 coverage + Verilator coverage) | EDA | iverilog, klayout, ngspice, verilator | MISLEADINGTwo names appear only in comments. | Step 4 uses verilator and iverilog. klayout and ngspice appear only in comments. | programs/vacuous_testbench_check.py:531; programs/l10_tb_conformance_check.py:1402 |
| 6FPGA early prototype + verification report audit | EDA | iverilog, klayout, openroad, verilator, yosys | MISLEADINGThe names are search strings, and the tool that actually runs is absent. | Step 6 builds with Quartus. The listed names are strings the audit looks for in a report. | programs/fpga_verification_audit.py:170; programs/design_one_shot_runner.py:17841 |
| 6, 9 | Programs | fpga_test_harness_gen, debug_first_pass (6); synth_wrapper_gen (9) | MISLEADINGThese programs are declared but never dispatched. | Nothing in the flow runs these three. The producers are the runner functions step_fpga_compile and step_yosys_synth. | programs/design_one_shot_runner.py:17841, :16498 |
| P0Structural-RTL pre-flight (chip-AGNOSTIC structural gates) | EDA | — | MISLEADINGDerived from an empty program list. | P0’s verdict comes from the structural umbrella. One of its programs compiles and runs iverilog/vvp. | programs/flow_compliance_check.py:320, :1053; programs/protocol_reference_tb_pass_check.py:409, :426 |
| P0 | Programs | — | MISLEADINGHides the umbrella. A gate program was also added after publication. | P0 runs the 245-program structural umbrella (_STRUCTURAL_RTL_GATES). Since e2975ceff it also declares flow_step_output_content_check.py. | programs/flow_compliance_check.py:320; flow/phase1_phase2_phase3.yaml, step P0 |
| P0 | D3, D7 | missing, missing | MISLEADINGThese cells should read n/a. | P0 declares no outputs, and its own YAML ruling publishes P0 as NA for the artefact dimensions (D3, D7, D8). The page already shows n/a for P0’s D8. | flow/phase1_phase2_phase3.yaml, step P0 comment |
| Constraints, synthesis and DFT | |||||
| 7Constraint setup (SDC + PVT matrix) | EDA | openroad, opensta, yosys | MISLEADINGThe mentions say the tools are not used. | Step 7 invokes no EDA tool. l21_to_upf_emit notes that Yosys and OpenROAD do not consume UPF. | programs/l21_to_upf_emit.py:28–29, :73; programs/stage_on_pass_review.py:599 |
| 7 | D5 | done | MISLEADINGThe check covers dangling references and cycles only. | Step 7’s stage-1 clauses read the results of steps 2–6 and P0, but step 7 declares blocks_on [1] only. The gap is soft, because both clauses are advisory. | flow/phase1_phase2_phase3.yaml, step 7; programs/stage1_compliance.py |
| 8SDC validation | EDA | openroad | MISLEADINGDocstring mention. | Step 8 invokes no EDA tool. | programs/derived_clock_sdc_required_check.py:16 |
| 9Synthesis (Yosys → mapped netlist) | EDA | abc, klayout, openroad, yosys | MISLEADINGklayout and openroad come from docstring examples. | Synthesis uses yosys and abc. | programs/provenance_check.py:18, :48–49; programs/design_one_shot_runner.py:16498 |
| 10Pre-layout STA (multi-corner) | EDA | — | MISLEADINGOmits the tool that produces the outputs. | Step 10 runs OpenSTA, multi-corner, through the Phase-3 runner (mcp_tools [eda_sta]). | programs/phase3_one_shot_runner.py:55452–55464, :61172 |
| 11DFT insertion (scan chain + ATPG + at-speed + BSDL) | EDA | iverilog, openroad, yosys | MISLEADINGopenroad is comment-only, and the ATPG engine is missing. | Step 11 runs Fault (cut, chain, atpg), which drives iverilog and yosys. OpenROAD is not used. | programs/fault_atpg_run.py:214, :1921–1952, :2172 |
| 11 | Programs | 4 programs | MISLEADINGThe scan inserter is omitted. | fault_scan_chain_insert.py is dispatched as Step 11a and writes scan_netlist.v, so 5 programs run. | programs/design_one_shot_runner.py:19960–19982 |
| DT1Transition-delay-fault (at-speed LOC) ATPG | EDA | abc, iverilog, opensta, yosys | MISLEADINGabc is a log-parser token and OpenSTA appears only in docstrings. | DT1 runs Fault cut and Yosys. ABC and OpenSTA are not invoked; OpenSTA first runs at DT2. | programs/transition_fault_atpg_run.py:1078, :763–764, :941–942 |
| 12Post-DFT optimization (resynth / buffering) | EDA | — | MISLEADINGOmits the tool that produces the output. | Yosys (opt_clean -purge) produces post_dft_netlist.v. | programs/design_one_shot_runner.py:20574–20583 |
| 13Equivalence check (RTL ≡ post-DFT netlist) | Programs | lec_equivalence_check.py | MISLEADINGThe producer is omitted. | lec_run.py (Yosys equiv) writes reports/lec.json and lec.rpt, and lec_equivalence_check.py then parses them. | programs/lec_run.py:152–153; programs/design_one_shot_runner.py:20657–20661 |
| 14Synthesis handoff gate (pre-PnR Yosys script + netlist audit; open-source-flow specific) | EDA | “11 programs” abc … yosys | MISLEADINGText matches in an auditor, and the list is mislabelled as programs. | Step 14 runs no EDA tool. The 11 names are text in flow_compliance_check.py, which spawns only Python programs. The label should read “11 tools”. | programs/flow_compliance_check.py:3232, :5968 (spawns Python programs only); programs/stage_on_pass_review.py:23 |
| 14 | Programs | 5 programs | STALEChanged by e2975ceff. | Now 6 programs: flow_step_output_content_check.py is a blocking gate program. | flow/phase1_phase2_phase3.yaml, step 14 gate |
| 14 | D5 | done | MISLEADINGCompleteness was never checked. | Step 14 reads stage_analog_compliance.json, a verdict over A1–A9, but no A-step is its ancestor. There are no dangling references or cycles, but the missing edge makes D5 partial. | flow/phase1_phase2_phase3.yaml, step 14 blocks_on [9, 13]; programs/flow_dependency_graph_check.py:22–33 |
| 14 | D8 | missing: “no blocking catcher for declared outputs” | STALEChanged by e2975ceff. | Now done: a missing netlist.v or stage_analog report fails the blocking content clauses. | programs/flow_gate_grid.py:218–227 (grid now lists no uncaught outputs) |
| DT2Path-delay-fault (at-speed, timing-graded) ATPG | Inputs → outputs | IN — | MISLEADINGHides declared dependency artefacts. | DT2 declares (condition_kind dependency_required) that it consumes DT1’s transition_coverage.json and step 22’s post-route SPEF. | flow/phase1_phase2_phase3.yaml, step DT2 condition |
| DT3Small-delay-defect (SDD) at-speed grade | Inputs → outputs | IN — | MISLEADINGHides declared dependency artefacts. | DT3 consumes DT2’s path_delay_coverage.json and DT1’s transition_coverage.json. | flow/phase1_phase2_phase3.yaml, step DT3 condition |
| Analog design and verification | |||||
| A1Analog Spec Extraction | Programs | analog_a1_spec_extract_check.py | MISLEADINGThe producer is omitted. | analog_a1_spec_emit.py runs first, then the checker. | programs/analog_one_shot_runner.py:808–811, :1496–1507 |
| A1 | AI role | “AI selects topology, then checks the emitted topology.” | WRONGThis describes A2. | When spec_gap.json records a decline, AI extracts the analog spec from L1/L5 (analog-spec-extract), and a signed judgement then covers spec.json. | programs/analog_one_shot_runner.py:821, :1128; flow/phase1_phase2_phase3.yaml, step A1 skills |
| A2Analog Topology Selection | Programs | analog_a2_topology_select_check.py | MISLEADINGThe producer is omitted. | analog_a2_topology_emit.py runs first, then the checker. | programs/analog_one_shot_runner.py:824, :1496–1507 |
| A2 | AI role | “AI sizes devices, then checks simulation evidence.” | WRONGThis describes A4. | When topology_gap.json records a decline, AI selects the topology (analog-topology-select), and a signed judgement then covers the topology artefacts. Sizing and corner simulation belong to A4. | programs/analog_one_shot_runner.py:835, :1129; programs/ai_signed_judgement.py |
| A3Analog Netlist Generation | EDA | netgen, ngspice | MISLEADINGnetgen appears in a comment, and ngspice as a file-name marker. | ngspice runs at A3 only inside the unlisted producer analog_a3_netlist_emit.py --verify-sim. netgen does not run at A3. | programs/analog_a3_netlist_emit.py:2078, :2164; programs/analog_a3_netlist_gen_check.py:145 |
| A3 | Programs | 2 checkers | MISLEADINGThe producer is omitted. | 3 programs run: analog_a3_netlist_emit.py plus the two checkers. | programs/analog_one_shot_runner.py:838, :857 |
| A3 | AI role | none: “Program-owned step” | MISLEADINGA3 follows the same gap-to-skill path as A1 and A2. | When netlist_gap.json records a decline, AI authors the netlist (analog-netlist-gen) and no signed judgement follows. | programs/analog_one_shot_runner.py:838–849, :1130, :1538–1543; programs/ai_signed_judgement.py:19 |
| A7, A8 | AI role | none: “Program-owned step” | MISLEADINGAI skills author the outputs, without a signed judgement. | On a non-stub run, analog-extraction-resim (A7) and analog-hardmacro-gen (A8) author the declared outputs, and no signed judgement follows. Only the verdict is program-owned. | flow/phase1_phase2_phase3.yaml, step A8 (lines 4195–4198); programs/analog_one_shot_runner.py:659–700 |
| A8Hardmacro Generation (LEF + Liberty + GDS + Verilog) | EDA | klayout, magic, netgen, ngspice, openroad | MISLEADINGFour of the names are comment or docstring mentions. | Only magic runs at A8, through analog_hardmacro_gds_emit. | programs/analog_lef_gds_outline_check.py:426–427; programs/analog_macro_rtl_interface_check.py:15, :35 |
| A8 | D5 | done | MISLEADINGAn edge to the phase-2 RTL is undeclared. | A8’s blocking analog_macro_rtl_interface_check reads the phase-2 RTL/netlist, but A8’s only ancestors are D1 and A1–A7. With no RTL present, the check returns 2, which becomes VACUOUS_PASS. | programs/analog_macro_rtl_interface_check.py:182–183; flow/phase1_phase2_phase3.yaml, lines 4278–4289 |
| Physical implementation and sign-off | |||||
| 15Floorplan + PDN | EDA | magic, openroad, opensta, yosys | MISLEADINGyosys and magic do not run here. | openroad (with OpenSTA embedded). yosys and magic appear only in comments. | programs/stage_on_pass_review.py:20–23; programs/ip_integration_check.py:159, :231 |
| 15 | Programs | 6 programs, including phase3_backend_step.py | MISLEADINGOne listed program is a declared no-op. | phase3_backend_step.py prints [SKIP] and returns 0, and no runner calls it. The working programs are the other five plus phase3_one_shot_runner.step_pnr. | programs/phase3_backend_step.py; programs/flow_declared_producer_run.py:22–37 |
| 15 | D5 | done | MISLEADINGA data edge is undeclared. | On the chip path, step_pnr runs io_pad_chip_top_gen (a 15.5ic program) before the floorplan. Its chip top and die_required_um feed step 15, yet the graph declares only 15 → 15.5ic. | programs/phase3_one_shot_runner.py:36277–36284; flow/phase1_phase2_phase3.yaml, line 4870 |
| 17Placement (global + detailed) | Inputs → outputs | OUT placed.def | STALEChanged by 4e36f3703 / fd809a4c9. | OUT is now placed.def plus reports/phase3/placement_legality.json. | flow/phase1_phase2_phase3.yaml, step 17 required_outputs |
| 18Spare-cell + ECO-prep insertion (Design-for-ECO) | EDA | — | MISLEADINGOpenROAD places the spare cells. | openroad places the spare instances inside the PnR TCL (mcp_tools [eda_pnr]). | programs/phase3_one_shot_runner.py:22813–22855 |
| 21Routing (global + detailed) | EDA | klayout, magic, openroad | MISLEADINGThese report formats are parsed, but the tools do not run here. | openroad detailed_route runs at step 21. KLayout and Magic formats are parsed by a shared program but belong to the step-31 sign-off DRC. | programs/drc_report_check.py; programs/phase3_one_shot_runner.py:59120, :59131 |
| 22Parasitic Extraction (RC → SPEF) | EDA | klayout, magic, openroad | MISLEADINGklayout comes from a usage example. | openroad (OpenRCX) and magic. | programs/provenance_check.py:49 |
| 22 | Inputs → outputs | OUT SPEF only | STALEChanged by 4e36f3703 / fd809a4c9. | OUT is now the SPEF plus reports/phase2/gates/spef_extraction.json. | flow/phase1_phase2_phase3.yaml, step 22 |
| 23Post-route STA (multi-corner multi-mode sign-off) | EDA | netgen, openroad, opensta | MISLEADINGnetgen appears in a docstring about LVS. | openroad and opensta. | programs/sta_corner_record_completeness_check.py:559 |
| 25EM check (electromigration lifetime) | EDA | — | MISLEADINGOpenROAD PSM is omitted. | OpenROAD PSM (analyze_power_grid -enable_em) produces the step-25 data. Row 24, fed by the same call, lists openroad. | programs/phase3_one_shot_runner.py:57725, :64527, :64562 |
| 26Antenna check (gate-oxide protection) | D5 | done | MISLEADINGThe step reads a downstream output. | The conditional gds_antenna_deck_check reads step 37’s GDS. Because 26 is an ancestor of 37, that edge cannot be declared without creating a cycle. | programs/gds_antenna_deck_check.py:67–71, :267 |
| 26.5icDie Finishing — seal ring + die identification (chip/IC path only) | EDA | klayout, magic | MISLEADINGmagic appears in a comment. | klayout only. | programs/die_finishing_gen.py:1175 |
| 26.5ic | D5 | done | MISLEADINGThe GDS dependency is missing. | die_finishing_gen reads and rewrites the streamed GDS, including step 37’s output, but 37 is not an ancestor of 26.5ic. | programs/die_finishing_gen.py:199–202, :1154–1160 |
| 27Signal Integrity (Crosstalk / Noise / Glitch + MCF crosstalk-delay) | Programs | si_crosstalk_check, si_mcf_sta_check | STALEChanged by e2975ceff. | Now 3 gate programs: si_crosstalk_check (blocking), flow_step_output_content_check (blocking) and si_mcf_sta_check (optional). | flow/phase1_phase2_phase3.yaml, step 27 gate |
| 28PERC / Reliability sign-off (ESD + latch-up + cross-domain) | EDA | klayout | MISLEADINGThe name is in a comment about another tool’s code. | Step 28 invokes no EDA tool. It consumes earlier verdicts. | programs/perc_signoff_check.py:216; programs/phase3_one_shot_runner.py:68183 |
| 29Post-Layout Gate-Level Simulation (Post-Sim + SDF) | EDA | — | MISLEADINGOmits the tools the runner uses. | openroad (write_sdf), plus iverilog and vvp (sdf_gate_sim). | programs/phase3_one_shot_runner.py:58316–58339; programs/sdf_gate_sim.py:1003, :1022 |
| 31Physical Verification (DRC + LVS + ERC + Density) | Step (section) | Physical implementation and sign-off | STALEChanged by ac2104931 (PR #2635). | Step 31 is now in stage4 (Output and handoff) and runs after GDS step 37. | flow/phase1_phase2_phase3.yaml, step 31 stage and blocks_on |
| 31 | EDA | klayout, magic, netgen, openroad, yosys | MISLEADINGyosys appears only in a comment and a string. | klayout, magic, netgen, and openroad (for ERC). yosys is not invoked. | programs/erc_density_check.py:376; programs/lvs_triage_classify.py:69; programs/phase3_one_shot_runner.py:67080–67170 |
| 32Post-route timing repair pass (multi-corner repair_design + repair_timing + reroute) | EDA | — | MISLEADINGOmits the tool the runner uses. | The runner drives OpenROAD (repair_design, repair_timing) and re-measures with OpenSTA. The only declared program names no tool. | programs/phase3_one_shot_runner.py:60507 |
| 32 | Programs | postroute_timing_repair_audit.py | STALEChanged by e2975ceff. | Now 2 programs, adding flow_step_output_content_check.py. | flow/phase1_phase2_phase3.yaml, step 32 gate |
| Output and handoff | |||||
| 34Metal Fill (ECO-aware density fill insertion) | EDA | klayout, openroad, yosys | MISLEADINGyosys appears in a docstring. | klayout and openroad. | programs/spare_cell_preservation_check.py (module docstring); programs/metal_fill_emit.py:58, :61 |
| 35DFM screen (CMP density + redundant-via ratio + foundry-side OPC/RET disclosure) | EDA | klayout, openroad | MISLEADINGThe names appear in docstrings and message strings. | Step 35 invokes no EDA tool. | programs/dfm_screen_check.py:29, :462, :475 |
| 35 | Programs | dfm_screen_check.py | STALEChanged by e2975ceff. | Now 2 programs, adding flow_step_output_content_check.py. | flow/phase1_phase2_phase3.yaml, step 35 gate |
| 36Tapeout checklist (final sign-off confirmation) | EDA | netgen | MISLEADINGThe step reads netgen output; it does not run netgen. | Step 36 invokes no EDA tool. It grades netgen’s report text. | programs/tapeout_checklist_gen.py:36, :47, :120 |
| 36 | D5 | done | WRONGThe step consumes artefacts from steps that are not upstream. | tapeout_checklist_gen treats step 38’s outputs as blocker rows, yet 38 is not upstream of 36. At publication, 36’s blocking tapeout check also needed the GDS from step 37, which was then declared downstream. | programs/tapeout_checklist_gen.py:88–90, :365–367; programs/phase3_one_shot_runner.py:68887–68898 |
| 37GDSII output (only if Step 31 PV fully clean) | Step (name) | “GDSII output (only if Step 31 PV fully clean)” | STALEChanged by ac2104931. | The name is now “GDSII output (after routed-layout pre-stream admission)”, and PV (step 31) now follows GDS. | flow/phase1_phase2_phase3.yaml, step 37 name |
| 37 | EDA | klayout, magic, netgen, openroad, opensta, yosys | MISLEADING4 of the 6 are text matches. | klayout and magic. The step_gds path shows no openroad, yosys, netgen or OpenSTA invocation. | programs/reported_figure_artifact_backing_check.py:415; programs/phase3_one_shot_runner.py (step_gds) |
| 37 | Programs | 10 programs | STALEChanged by ac2104931. | Now 11 programs, adding layout_receipt_identity_check.py (blocking). | flow/phase1_phase2_phase3.yaml, step 37 gate |
| 37 | Inputs → outputs | 4 outputs | STALEChanged by ac2104931. | Now 5 outputs, adding reports/phase3/layout_receipts.json. | flow/phase1_phase2_phase3.yaml, step 37 required_outputs |
| 37.3GDS stream-out / finishing fidelity — the shipped GDS XOR'd against this run's own pre-finishing boundary | EDA | klayout, magic | MISLEADINGmagic appears only in comments. | KLayout only. | programs/gds_xor_check.py:273, :941 |
| 37.4Sign-off metrics aggregation — the run's own checker verdicts, under the names the release documents read | EDA | klayout, magic, netgen, openroad, opensta | MISLEADINGThe names are report-selector strings. | The step is pure aggregation and invokes no EDA tool. | programs/signoff_metrics_aggregate.py:939–944 |
| 37.4 | D5 | done | WRONGThe step reads outputs of steps that are not upstream. | signoff_metrics_aggregate reads 37.3’s gds_xor.json, but 37.3 is not upstream of 37.4, either at publication or now. Since ac2104931, step 31’s DRC and LVS outputs are not upstream either. | programs/signoff_metrics_aggregate.py:700, :718–734 |
| 37.5ipDigital Hardmacro Generation — LEF + Liberty + GDS + Verilog (delivered on EVERY route) | EDA | magic, openroad, opensta | MISLEADINGopenroad appears in a comment. | magic and opensta. | programs/digital_hardmacro_gen.py:1622, :1820, :1894 |
| 37.5icTape-out Precheck — our general ladder, plus the operator's own refusal where the PDK ships one (chip/IC path only) | EDA | klayout, magic, openroad | MISLEADINGThe names are comment and string matches. | The plugin source invokes no openroad for this step. klayout and magic run, if at all, inside the operator’s precheck container. | programs/tapeout_precheck.py:161–163; programs/tapeout_readiness_check.py:605–631 |
| 37.5ic | D5 | done | STALEChanged by ac2104931. | On current main, the edge to PV step 31 is missing: general_precheck reads step 31’s DRC and LVS outputs, but 31 is no longer an ancestor of 37.5ic. | programs/general_precheck.py:1146–1150 |
| 38Foundry Handoff (mask spec + WAT plan + scribe layout + corner test kit) | EDA | klayout, openroad, verilator, yosys | WRONGNeither program starts a process. | Step 38 invokes no EDA tool; it parses reports that Yosys and OpenROAD already wrote. The cell should read —. | programs/foundry_handoff_pack_gen.py and programs/foundry_handoff_package_check.py (0 subprocess calls) |
| 39FPGA final sign-off (recompile + on-board test) | EDA | opensta, yosys | WRONGThe names are comments in a program that starts no subprocess. | Step 39’s programs invoke no open-source EDA tool, and the bench toolchain logs are only read. The cell should read —. | programs/stage_on_pass_review.py:23; programs/stage4_compliance.py |
| 39 | Programs | 7 programs | MISLEADINGNothing in the flow runs 3 of the 7. | 4 are wired: fpga_on_board_attestation_check blocks and 3 are advisory. The two SignalTap checks run only when the agent calls them, and bringup_plan_gen is run by nothing. | flow/phase1_phase2_phase3.yaml, step 39 (lines 9176–9186) |
| Mixed-signal integration | |||||
| M1Mixed-Signal Top-Level Integration (A+D GDS merge + macro placement) | EDA | klayout, magic, netgen, openroad | WRONGopenroad is comment-only. | klayout, magic and netgen. | programs/mixed_signal_top_lvs_run.py:96, :802, :832, :886 |
The skeptic found the table correct for these findings. They are listed only as counts per column.
| Column | Refuted | Why the cell stood |
|---|---|---|
| Inputs → outputs | 20 | The row equals the declared required_inputs and required_outputs. Undeclared reads and writes are gaps in the flow’s declarations. They belong to D5 and D7, not to this column. (DT1, A6, A7, A8, A9, 20, 26.5ic, 28, 29, 30, 31, 32, 36, 37.3, 38, 39, 40–44, M2, M3, M4.) |
| Programs | 9 | The row equals the YAML-declared program set, and programs the runner dispatches without declaring them are a gap in the flow’s declarations (D1, A4, A5, A6, A7, A8, 15.5ic, 29, 32). |
| AI role | 8 | The page defines this column as role assignments for eight signed-judgement hand-offs. Step 5’s text matches its formal-verify skill. Elsewhere, advisory reviews and failure-triggered repair skills do not make a step AI-judged (5; 2, 7; 6, 9; 20, 23, 24, 25, 27, 30; 31; 32; 33; 39). |
| EDA | 3 | The tool really runs on a declared skill or runner path (A5, A6), or the program parses that tool’s real reports (30). |
| D7 | 2 | “missing” is the right state (7; 38, M1). |
The skeptic re-checked 73 cells that the reviewers had accepted, and 72 held. The one that did not is the D3 sample for rows D1–9: it held for 11 rows, but P0 should read n/a, which is the confirmed finding above. The step 37.3 D5 cell holds on current main. By the reviewer’s account it was wrong when published, because blocks_on [21] then lacked step 37, whose GDS it XORs. For rows 10–A3 and 31–37.5ic, the skeptics accepted the D9 “missing” cell on the grid’s stated basis without running the D9 ledger test. The other four groups ran that test and confirmed D9 as MISLEADING.
| Rows | Held | Cells sampled |
|---|---|---|
| D1–9 (12 rows) | 12 of 13 | EDA 0.5ic, 3, 5; Programs D1; D5 (10 rows); AI role D1, 1, 4; D2 6; D8; D4; I/O 8. The D3 sample held for 11 rows. P0 should read n/a, which is the confirmed finding above. |
| 10–A3 (12 rows) | 14 of 14 | I/O 11, 13, A1, A3; EDA FS1, DT2; D5 10; D8 12, FS1; D2 13; D6 DT2; D3; D9 (accepted on the grid’s stated basis); AI role 11. |
| A4–19 (12 rows) | 12 of 12 | D1, D3, D4, D8 on all 12; AI role A9, 16; D6 and EDA 15.5ic; I/O 19; Programs A9; D5 A4; NDA scan. |
| 20–30 (12 rows) | 12 of 12 | Programs 23; I/O 21, 25; D6 26.5ic; D1, D3; EDA 24, 26; D5 25; D2 20; AI role 28; NDA scan. |
| 31–37.5ic (11 rows) | 12 of 12 | Programs 31; OUT 31; EDA 33; I/O 34, 37.5ic; AI role 36; D5 37.3; D6 37.5ip; D1, D3, D9 (accepted on the grid’s stated basis); D2 on 9 rows. |
| 38–M4 (11 rows) | 10 of 10 | EDA 40–44, M2–M4; Programs M2; D8 38; D2 39; D5 all; I/O M1; D3 40–M4; D1 41; AI role; NDA scan. |
condition key, but the page defines D6 to include conditional skips and vacuous passes. 18 of the flagged steps have clause-level condition_files_exist with a declared reason, and the other 18 have rc=2 → VACUOUS_PASS or skip tiers. The plugin’s D6 ledger has no NA cell, and where it was run (28 of the 36 steps) it marked these cells ENFORCED. Separately, all 20 D6 “partial” cells are STALE and now read done.programs/tests/test_matrix_d9_verdict_consumed.py, which decides the page’s D9 chain from source; it passed for all 47 rows tested. The remaining 23 rows were not tested against it in this review.