AI-Native IC Design Platform

Design chips with
natural language

From your first prompt to production-ready GDS — fully AI-driven. No IC design experience required. 135 ICs validated end-to-end.

Get Started View Source
43Plugin Skills
135ICs Validated
98%Design Automated
14Open EDAs Used

Three-phase flow

Every IC starts from a natural-language prompt and ends with a production-ready GDS.

01

Specification

Prompt → Spec → Documents

  • Natural language prompt
  • AI-guided dialog (2–5 rounds)
  • 10-section Datasheet
  • 8-section Application Note
  • Cross-document consistency check
Checkpoint 1 — Quality ≥ 70/100
02

Design & Silicon

RTL → Synthesis → Layout → GDS

  • SystemVerilog RTL generation
  • SVA formal assertions (8+)
  • Yosys synthesis + PDK mapping
  • OpenROAD place & route
  • KLayout GDSII output
Checkpoint 2 — DRC clean, cells > 0
03

FPGA Verification

BIST → Coverage → Production

  • Executable SOF with BIST engine
  • 6-layer coverage analysis
  • UART / LED / HPS test methods
  • Fmax sweep & stress loop
  • Automated fail diagnosis
Checkpoint 3 — All tests PASS

43 plugin skills

Each skill is a domain expert guiding one step of the IC design flow.

Frontend — 13 skills
spec-to-rtlrtl-reviewrtl-repairassertion-gentestbench-genformal-verifyequivalence-checkcdc-checkrdc-checkcoverage-closureppa-predicthls-c2rtlsynth-wrapper-gen
Backend — 10 skills
dft-insertupf-authorplacement-optimizects-plansta-reviewdrc-fixlvs-triageir-drop-triageeco-plantapeout-checklist
Methodology — 14 skills
prompt-intakedatasheet-genschematic-gencheckpoint-gateflow-orchestratesynth-doctorspec-validatorfpga-test-harnessfpga-signaltapfpga-hps-bridgespec-reviewarchitecture-exploreregression-manage
Silicon & Analog — 6 skills
analog-sizinganalog-layoutams-simatpgbringup-planyield-diagnostic

Technology stack

Open-source tools, open PDKs, open AI — no vendor lock-in.

EDA Tools

Yosys, OpenROAD, KLayout, SymbiYosys, OpenSTA, Verilator, ngspice, Fault, Netgen — 14 tools total

Process Nodes

GF180MCU 180nm (3.3V) and SKY130 130nm (1.8V) — both open-source PDKs

FPGA Target

Intel Cyclone V on DE10-Nano — Quartus 23.1, BIST + UART + HPS verification

AI Engine

Claude Code + MCP Server — 14 EDA tools wrapped as callable functions

Quality

367 unit tests, CI pre-commit hooks, synth-doctor, pnr-doctor, spec-validator

Knowledge Base

PostgreSQL + pgvector — 489 ICs, 28 manufacturers, semantic search

135-IC validation

The industry's first AI-driven end-to-end design campaign across 135 ICs and 28 manufacturers.

135/135 Spec + Documentation

Datasheet and Application Note for every IC

135/135 Synthesis PASS

GF180MCU 180nm + SKY130 130nm PDK

97% DRC Clean

First-pass zero violations

805K Largest Design

RISC-V BMC SoC — zero IP licensing

Traditional IC Design

  • 10+ years experience required
  • $1M+ commercial EDA tools
  • NDA-locked PDK
  • 6–12 months design cycle
  • $100K+ per tapeout
vs

Vibe-IC

  • Anyone — natural language
  • Open-source EDA (Yosys, OpenROAD)
  • Open PDK (GF180, SKY130)
  • 2–3 months incl. tapeout
  • $10K (Efabless chipIgnite)

Get started

Three commands to your first AI-designed IC.

01
Launch EDA environment
docker run -d --name iic-eda \
  -v "$PWD:/foss/designs:rw" \
  hpretl/iic-osic-tools:latest
02
Install MCP server
cd mcp-eda-server && npm install
claude mcp add eda-tools \
  node $PWD/src/index.js
03
Start designing
"Design a temperature sensor IC
 with I2C interface, 12-bit,
 alert output, SOIC-8 package"
View on GitHub

MIT License — Free and open source