Disclaimer

Last updated: April 10, 2026

1. Design Output Disclaimer

All IC design outputs produced by the Platform (including but not limited to RTL, Netlist, DEF, GDS, Datasheet, Application Note) are AI-generated and have not been reviewed by professional IC design engineers.

Users must engage qualified IC design engineers for a complete review before any tapeout or production.

2. 135-IC Validation Scope

The Platform's claim of "135 ICs validated" means:

Yosys synthesis passed: RTL can be synthesized into a gate-level netlist, but this does not guarantee functional correctness
DRC passed: Layout complies with PDK design rules, but this does not mean it is ready for tapeout
FPGA BIST passed: Basic functional tests passed, but coverage is limited

The above validations are not equivalent to:

Full functional simulation passing
Timing closure across all corners
EMC/EMI testing passed
Reliability qualification passed
Production ready

3. ARM IP Notice

The Platform's Aspeed BMC IC designs (#121-134) implement only the peripheral subsystem RTL and do not include ARM CPU cores. ARM Cortex-A35/A7/M4F and other CPU cores require a separate license from ARM Ltd. The Platform provides a RISC-V open-source alternative (IC #135, 805,830 cells, zero licensing fees).

4. Open Source Tools Disclaimer

The EDA tools used by the Platform (Yosys, OpenROAD, KLayout, etc.) are maintained by open-source communities. The Platform does not provide any guarantee regarding the correctness, stability, or fitness for purpose of these tools.

5. Investment & Business Decisions

Information provided by the Platform does not constitute investment or business advice. Estimates of tapeout costs, timelines, and yield are for reference only.

6. Liability Cap

To the maximum extent permitted by law, vibeic.ai and its affiliates shall not be liable for any direct, indirect, incidental, special, or consequential damages arising from the use of the Platform.

7. Contact

If you have any questions, please contact contact@vibeic.ai.