序 · Preface
Preface: four months of building, and why I'm open-sourcing now
The series' preface — the origin story from March 2026, the philosophy that grew out of the failures, why I'm open-sourcing now, and an honest disclosure of the two things not yet proven: no IC-design expert has reviewed it, and no commercial EDA has cross-checked it. Plus a risk warning for the industry, and an open invitation.
01 / 12
Handing the whole chip-design flow to AI: one software person's end-to-end bet
What Vibe-IC is, and the bet behind it — a software veteran, new to the IC flow, hands the whole chip-design process to AI: one AI-Native, end-to-end flow where open-source and commercial tools are equally welcome.
02 / 12
First principles: logical work will eventually be done by AI — why IC design is next in line
First principles: work that is logical can be learned, repeated, and eventually done — and surpassed — by AI. IC-design experience is mostly logical, which is why the roles in IC design are very likely next in line.
03 / 12
Open, commercial, and a paid ecosystem where both coexist
EDA is almost a gimme: if commercial software can do it, open source can too. And this was never about beating anyone — open or commercial, both are welcome to plug into the ecosystem, users paying to use them just like paid IP.
04 / 12
The architecture at a glance: four months, three parts, one end-to-end flow
The whole project in one map: four months, three parts — build the flow, converge the front end with benchmarks, converge the back end with the EDA tools. The next three posts go deep on each.
05 / 12
Part 1 — Building the flow: Phase / Stage / Step, main line + analog + mixed-signal (the ATLAS method)
Part 1 — building the flow: Phase 1/2/3, L1–L27, dozens of steps, a main line plus analog and mixed-signal branches, and the ATLAS method that keeps it converging. Each step is one transformation plus one checking gate.
06 / 12
Part 2 — Front-end convergence: benchmarking Spec→RTL to a clean pass (Program-First / AI-Backup / IC-expert extraction)
Part 2 — front-end convergence: benchmarking Spec→RTL until it passes cleanly. Three principles — score-optimize, Program-First with AI-Backup dual-track convergence, and distilling experience into the IC-expert agent.
07 / 12
Part 3 — Back-end convergence: making every step after RTL pass (EDA: completing open source, coexisting with commercial)
Part 3 — back-end convergence: making every step after RTL pass. Tools as AI's hands, forking open source to complete it to sign-off grade (commercial welcome to coexist), and an honest, per-tool gap table.
08 / 12
Fixing the open tools: a few war stories from forking EDA
A candid, behind-the-scenes piece: three war-stories from actually fixing the open-source EDA tools — the native SVRF DRC engine, an OpenROAD post-route crash, a leaner adder — each a reproducible FAIL→PASS.
09 / 12
Honesty is the moat: anti-fabrication, deterministic gates, and the holes I fell into
Honesty is the moat. A confident fake PASS can get someone killed in silicon, so honesty is made structural: deterministic gates, real artifacts, no gate certifies itself — plus the 30/30 → 0/10 re-scoring and the governance hole I fell into.
NOTES
Checks that lie: how we verify the gates are actually guarding
Two blocking gates returned pass over an empty directory while printing "NOT screened". The nine questions we ask of all 63 flow steps, twelve catalogued shapes of lying, and the census that replaced finding them one collision at a time — including how the census itself was calibrated.
10 / 12
Closing the loop: FPGA verification that tunes itself, 24/7
Why closed loops — not sequenced steps — are the heart of automating an IC flow, walked through a real FPGA-verification loop: program a board, read its LEDs with a camera, and re-run until it converges, unattended. Plus the single-step and cross-step loops that run the whole flow.
11 / 12
Field notes: which LLM drives the flow — and why Vibe-IC defaults to Claude
A first-person field note across Claude, Kimi, and GPT/Codex, updated with the 2026-08-16 GPT-5.6-Sol + Vibe-IC v1.10.45 run: VE-v2 153/156 single-shot; VE-Human 153/156 single-shot → 154/156 after one repair round; RTLLM 48/50 single-shot → 49/50 after one repair round. The new GPT figures are model-plus-plugin datapoints, not a model-only A/B; older run identities are stated only to the level their evidence supports.
12 / 12
CTA: The AI-Native world, and how we build it together
Where this goes, and how we build it together: an end-to-end world where a prompt becomes silicon with no hand-offs in between — and an open invitation to veterans, software engineers, students, and tool vendors alike.
番外篇 · Bonus
Bonus: Wild Guesses About the Future
A no-liability bonus note — one tech person's wild guesses about the world ten years into the AI wave: a turbulent transition, a productivity explosion, and IC design as the next step after software in the democratization chain.
About the author
Reyer Chu · 瞿孝洋A software veteran of many years who has led software teams. He has spent over a decade in the IC industry, including his time at MediaTek, but always on the software layer above — which left him a genuine newcomer to the actual IC-design flow. That gap is exactly why Vibe-IC was built AI-native, entirely in the open.
Special thanks
- Chialee Wei
- Allen Lin
- SC Liu
More names to come — this list grows as more people join the journey.