The vibeIC Series
Ten articles on how we built an AI-Native IC design platform — from MCP server to silicon. Citing commit hashes, file paths, version numbers. No hype.
01 / 10 · CALL FOR CONTRIBUTORS
Why IC Design Needs an AI-Native Open Platform
The three walls that have locked IC design for 20 years — and why AI is finally good enough to tear them down. Plus: we're inviting you to help.
02 / 10 · COMING SOON
The Three-Phase Closed Loop: prompt → L1–L13 → RTL → FPGA → GDS → Silicon
Canonical flow, two entry points, 50 skills layered.
03 / 10 · COMING SOON
MCP EDA Server: 46 EDA + Device tools as one LLM-callable protocol
Why MCP, not a framework.
04 / 10 · COMING SOON
Device Framework: drop folder, restart server, done
_registry.js auto-registration, three vendor cases.
05 / 10 · COMING SOON
Real closed loop: FPGA + Camera + Scope, one AI
bring-up loop, reference IC 5/5, 9-bug battle.
06 / 10 · COMING SOON
No silent PASS: 350 deterministic programs + 5 anti-fabrication doctrines
Structural gates, provenance hashes.
07 / 10 · COMING SOON
Wave 32: 36 FAILs and the governance hole we found
burn-FAIL-SOF war, CI sentinel, ECO guard.
08 / 10 · COMING SOON
Honest training: from 30/30 to 0/10
supervised mimicry vs honest dialogue.
09 / 10 · COMING SOON
Open Platform: five surfaces, chip-AGNOSTIC by code
plugin.yaml schema, trust tiers, backlog sanitize.
10 / 10 · COMING SOON
Future: standing on giants, rewriting IC design with the community
MIT, Efabless, SKY130, community manifesto.