2026-05-25 · Reyer Chu · vibeIC Series 01 / 10

Why IC Design Needs an AI-Native Open Platform — And Why We're Inviting You to Help Rewrite It

Design chips with natural language. From your first prompt to production-ready GDS — fully AI-driven. No IC design experience required.

— vibeic.ai

1. The IC design industry has been locked behind three walls for twenty years

If you have an idea for a chip today, you immediately hit three walls.

Wall #1 — Experience. Traditional IC design has a 10-year on-ramp. You need Verilog, SystemVerilog, RTL coding style, lint, CDC, formal verification, STA, DFT. You need to know the difference between Yosys and Design Compiler, debug setup violations you can't see, understand why PnR congests, and remember DRC, LVS, PERC, IR-drop, EM, antenna, ATPG. Without a decade of training, you can't even talk to the tools.

Wall #2 — Tool cost. A commercial EDA tool chain (Cadence / Synopsys / Mentor) starts at $1M USD/year. PDKs are locked behind NDA. The question "can I run synthesis" already excludes 99.9% of developers.

Wall #3 — Time and capital. Spec to tapeout is 6–12 months. An MPW shuttle costs $100K. One re-spin and you're done. The whole industry has been narrowed to a few hundred companies with enough capital to play.

The result: IC design is one of the few cutting-edge fields still stuck in artisan-craft mode. Our SaaS peers ship products in a day with Cursor + Claude. To make a chip, only a few hundred companies on the planet are even allowed to try.

vibeIC exists because AI is finally good enough to tear those walls down.

2. Can AI actually design chips? Yes — but only with the right infrastructure

The last two years produced a lot of "AI for chip design" demos. Most were LLMs wired to an RTL generator, producing a toy ALU, a paper, then silence. The problem was never "can the LLM write Verilog" — it can, and it gets better every month. The real problems:

• Design isn't just writing Verilog. A full chip walks 33 canonical steps across Phase 1 (spec) / Phase 2 (RTL+verify) / Phase 3 (signoff). Every step can fail. Every step needs reproducible evidence.
• EDA tools aren't chat interfaces. Yosys, OpenROAD, KLayout, ngspice, Magic, xschem, Verilator, SymbiYosys, cocotb — each has its own CLI, log format, failure modes. If the LLM can't see tool state, it can't close the loop.
• Hardware verification isn't just a testbench. An RTL that passes simulation will not run on FPGA, and definitely not on silicon. Without device-in-the-loop, AI is just scoring high in a sandbox.

vibeIC took a hard split from the "LLM-as-Verilog-generator" approach from day one. We're not building a prompt template. We're building the infrastructure that gives AI hands and eyes on real hardware.

3. vibeIC's three answers to the three walls

This isn't marketing. These are direct consequences of engineering choices: ship every EDA tool as one ~22 GB Docker image (hpretl/iic-osic-tools:latest); target GF180MCU + SKY130 as primary PDKs; wrap EDA tools with MCP (Model Context Protocol) so any LLM can call them; route tapeout through Efabless chipIgnite to land at $10K. Stack those choices and the walls fall.

4. The core doctrine: Dual Organic Growth — Standing on Giants

vibeIC's design philosophy is called Dual Organic Growth — Standing on Giants. It's the long-term theoretical base of the platform.

Axis 1 — AI Giant Grows (general capability). We build on the strongest AI in the world (Claude). Every time the underlying model advances a generation, vibeIC's conversation, spec extraction, RTL generation, and bug debugging all advance with it. We ride on a giant — when the giant grows, we grow. We do not waste time building "our own LLM."

Axis 2 — Open-Source Community Deepens (domain expertise). 350 deterministic programs come from real-world bug post-mortems — each program prevents one entire class of error. 50 AI skills, each a domain expert on one phase of design. 213 structural-RTL gates earned in real silicon bring-up. The deterministic part complements the LLM: the LLM generates and reasons; the deterministic gates enforce "no silent pass."

Stack both axes — AI capability × deterministic IC knowledge — and the platform compounds over time, without us having to rewrite code to benefit from each new model release.

This is the watershed between vibeIC and every other AI-EDA attempt: others try to replace EDA tools; we wrap them. Others fine-tune a small in-house model; we stand on the strongest model and write deterministic gates around it. Those are two completely different long-term trajectories.

5. Why open source, why MIT, why plugin

Why give it away for free?

Three layers of answer.

First — the industry needs to be opened. If vibeIC becomes another closed-source SaaS, we've just replaced Synopsys with vibeIC. The structural problem of IC design hasn't changed. To genuinely let anyone design chips, the tooling must be MIT-licensed, on GitHub, fork-able by anyone.

Second — community is the best source of deterministic gates. Every external bug post-mortem, every vendor device manifest, every IP house's ip_metadata makes vibeIC stronger. One person can't write 350 deterministic programs. 1000 people each writing one chip-AGNOSTIC gate can.

Third — plugin is the actual open-platform architecture. We're not "showing you our source code." We're "giving you a manifest schema — wrap your device, IP, or EDA tool as a plugin, drop it into the marketplace, every vibeIC user can call it immediately." Vendors don't wait for us to review PRs or cut releases. They ship plugins; they own them.

This directly maps to the five extension surfaces on /platform.html: Device Hardware, EDA Tools, IC IP Blocks, Partner Plugins, Community Backlog. Each is a plugin entry point.

6. Who this is for — not just IC engineers

Most people hear "IC design platform" and assume the user is a senior IC engineer. That is explicitly not our target.

vibeIC is built for:

• Founders with a product idea but no IC background. You don't need to know Verilog. You need to describe: "a temperature sensor IC, I2C interface, 12-bit resolution, alert output, SOIC-8 package."
• Students and makers who've been scared off by ASIC tooling. Tiny Tapeout at $100–300 + vibeIC's AI flow = you can actually tape out a chip that's yours.
• EDA / Foundry / IP vendors stuck behind a tooling moat. Wrap your tool as a plugin and reach every Claude Code user instantly.
• Academic researchers validating new processes, PDKs, or methodologies. The whole flow is open, reproducible, and guarded by 1902 pytest cases.

The goal is not "make IC engineers more efficient." The goal is "let people who aren't IC engineers design ICs." Two completely different markets — the second is 100× larger.

7. What's coming in the next nine articles

• Article 02 — The three-phase closed loop: prompt → L1–L13 → RTL → FPGA → GDS → Silicon
• Article 03 — MCP EDA Server: 46 EDA + device tools exposed as a protocol the LLM can call
• Article 04 — Device Framework: drop a folder, restart the server, done
• Article 05 — Real closed loop: FPGA + Camera + Scope, all controlled by one AI
• Article 06 — No silent PASS: 350 deterministic programs + five anti-fabrication doctrines
• Article 07 — Wave 32: a 36-FAIL war story and what we learned about governance holes
• Article 08 — Honest training: from 30/30 to 0/10 in the Phase-1 validation experiments
• Article 09 — The open platform: five extension surfaces, chip-AGNOSTIC by code
• Article 10 — Future: standing on giants, rewriting IC design with the community

Every article cites commit hashes, file paths, version numbers. No hype, no vapor, no "coming soon." Every feature referenced ships today on github.com/reyerchu/AI_IC_design, with tests and releases (latest v1.6.32, 2026-05-08).

vibeIC's mission in one sentence:

Lower the barrier from decades of training to a conversation.

8. We're inviting you — because what we're missing is you

vibeIC is not a one-person project.

The doctrine spells it out: "One person can't write 350 deterministic programs. 1000 people each writing one chip-AGNOSTIC gate can." The platform — plugin schema, MIT license, marketplace, chip-AGNOSTIC by code — is infrastructure built for contributors.

If you are any of the people below, please reach out:

🛠 IC / EDA veterans (10+ years)

The know-how you bled for shouldn't die in your head.

• Turn your "you only learn by stepping on it" bug patterns into deterministic programs
• Wrap your favorite EDA flow as an MCP plugin
• Wrap your IP blocks as ip_metadata plugins
• Your domain knowledge gets re-used by 1000 young engineers — not retired with you.

💻 AI / SaaS engineers

You don't need to know IC. Your skills fill exactly the gap we have.

• MCP server extensions, tool wrapping
• Plugin marketplace front-end/back-end, developer UX
• Observability, debugging UI, conversation analytics
• This is the first chance to bring the Cursor-class experience to silicon.

🎓 Students / aspiring IC designers

You are the most qualified user of vibeIC.

• Tape out your first chip via SKY130 / GF180MCU + Tiny Tapeout ($100–300)
• Turn your bring-up bugs into community contributions
• 1902 pytest cases + 350 deterministic programs — start by fixing your first failing test.

🏭 EDA / Foundry / IP / Device vendors

You don't have to open-source the product. You just ship a plugin.

• Your device → device manifest plugin
• Your IP → ip_metadata plugin
• Your EDA tool → MCP wrapper plugin
• Ship the plugin, every vibeIC user can call your tool immediately.

9. What we need most right now (concrete)

No politeness. Here's the truth:

10. How to start

Lowest-cost participation path:

1. Look at the repo: github.com/reyerchu/AI_IC_design — give it a star, run make test
2. Introduce yourself: open a GitHub Issue, tell us who you are and what you want to build
3. Pick a plugin track: browse /platform.html and pick the surface closest to your expertise
4. Reach me directly:

- X / Twitter: @vibeic_ai (launching) - Email: reyer@vibeic.ai - LinkedIn / personal FB: Reyer Chu (fastest response)

We're not building a product. We're rewriting the developer experience of IC design itself. If this article hits you, now is the best time to join — the platform is still small enough that your contribution will be visible, attributable, and meaningful.

Next article (02) walks the full three-phase closed loop — from one prompt to silicon, end to end.

— Reyer Chu / vibeic.ai